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ICST - (M1025 / M1026) VCSO BASED CLOCK PLL

Numéro de référence M1025
Description (M1025 / M1026) VCSO BASED CLOCK PLL
Fabricant ICST 
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M1025 fiche technique
www.DataSheet4U.com
Integrated
Circuit
Systems, Inc.
Product Data Sheet
M1025/26
VCSO BASED CLOCK PLL WITH AUTOSWITCH
GENERAL DESCRIPTION
PIN ASSIGNMENT (9 x 9 mm SMT)
The M1025/26 is a VCSO (Voltage Controlled SAW
Oscillator) based clock jitter
attenuator PLL designed for clock
jitter attenuation and frequency
translation. The device is ideal for
generating the transmit reference
clock for optical network systems
supporting up to 2.5Gb data rates.
It can serve to jitter attenuate a
stratum reference clock or a recovered clock in loop
timing mode. The M1025/26 module includes a
proprietary SAW (surface acoustic wave) delay line as
part of the VCSO. This results in a high frequency,
high-Q, low phase noise oscillator that assures low
intrinsic output jitter.
MR_SEL2
MR_SEL0
MR_SEL1
LOL
NBW
VCC
DNC
DNC
DNC
28 18
29 17
30
31
M1025
32 M 1 0 2 6
16
15
14
33
34 ( T o p V i e w )
13
12
35 11
36 10
P_SEL0
P_SEL1
nFOUT
FOUT
GND
REF_ACK
AUTO
VCC
GND
FEATURES
Integrated SAW delay line; low phase jitter of < 0.5ps
rms, typical (12kHz to 20MHz)
Output frequencies of 62.5 to 175 MHz
(Specify VCSO output frequency at time of order)
LVPECL clock output (CML and LVDS options available)
Reference clock inputs support differential LVDS,
LVPECL, as well as single-ended LVCMOS, LVTTL
Loss of Lock (LOL) output pin; Narrow Bandwidth
control input (NBW pin)
AutoSwitch (AUTO pin) - automatic (non-revertive)
reference clock reselection upon clock failure
Acknowledge pin (REF_ACK pin) indicates the actively
selected reference input
Hitless Switching (HS) options with or without Phase
Build-out (PBO) to enable SONET (GR-253) /SDH
(G.813) MTIE and TDEV compliance during reselection
Pin-selectable feedback and reference divider ratios
Single 3.3V power supply
Small 9 x 9 mm SMT (surface mount) package
SIMPLIFIED BLOCK DIAGRAM
Figure 1: Pin Assignment
Example I/O Clock Frequency Combinations
Using M1025-11-155.5200 or M1026-11-155.5200
Input Reference
Clock (MHz)
(M1025)
(M1026)
19.44 or 38.88
77.76
155.52
622.08
PLL Ratio
(Pin Selectable)
(M1025) (M1026)
8 or 4
2
1
0.25
Output Clock
(MHz)
(Pin Selectable)
155.52
or
77.76
Table 1: Example I/O Clock Frequency Combinations
M1025/26
Loop Filter
NBW
DIF_REF0
nDIF_REF0
DIF_REF1
nDIF_REF1
REF_ACK
REF_SEL
AUTO
4
MR_SEL3:0
MUX
0 R Div
1
PLL
Phase
Detector
0
1
Auto
Ref Sel
LOL
Phase
Detector
M/R Divider
LUT
M Divider
VCSO
P Divider
(1, 2, or TriState)
TriState
LOL
FOUT
nFOUT
2
P_SEL1:0
P Divider
LUT
Figure 2: Simplified Block Diagram
M1025/26 Datasheet Rev 1.0
Revised 28Jul2004
M1025/26 VCSO Based Clock PLL with AutoSwitch
Integrated Circuit Systems, Inc. Networking & Communications www.icst.com tel (508) 852-5400

PagesPages 14
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