PDF IDT71V433 Data sheet ( Hoja de datos )

Número de pieza	IDT71V433
Descripción	Synchronous SRAM
Fabricantes	IDT
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No Preview Available ! www.DataSheet4U.com 32K x 32 3.3V Synchronous SRAM Flow-Through Outputs IDT71V433 Features x 32K x 32 memory configuration x Supports high performance system speed: Commercial and Industrial: — 11 11ns Clock-to-Data Access (50MHz) — 12 12ns Clock-to-Data Access (50MHz) x LBO input selects interleaved or linear burst mode x Self-timed write cycle with global write control (GW), byte write enable (BWE), and byte writes (BWx) x Power down controlled by ZZ input x Single 3.3V power supply (+10/-5%) x Packaged in a JEDEC Standard 100-pin rectangular plastic thin quad flatpack (TQFP). Description The IDT71V433 is a 3.3V high-speed 1,048,576-bit SRAM orga- nized as 32K x 32 with full support of various processor interfaces including the Pentium™ and PowerPC™. The flow-through burst archi- tecture provides cost-effective 2-1-1-1 performance for processors up to 50 MHz. The IDT71V433 SRAM contains write, data-input, address and control registers. There are no registers in the data output path (flow- through architecture). Internal logic allows the SRAM to generate a self-timed write based upon a decision which can be left until the extreme end of the write cycle. The burst mode feature offers the highest level of performance to the system designer, as the IDT71V433 can provide four cycles of data for a single address presented to the SRAM. An internal burst address counter accepts the first cycle address from the processor, initiating the access sequence. The first cycle of output data will flow-through from the array after a clock-to-data access time delay from the rising clock edgeofthesamecycle. Ifburstmodeoperationisselected(ADV=LOW), the subsequent three cycles of output data will be available to the user on the next three rising clock edges. The order of these three addresses will be defined by the internal burst counter and the LBO input pin. The IDT71V433 SRAM utilizes IDT's high-performance 3.3V CMOS process, and is packaged in a JEDEC Standard 14mm x 20mm 100-pin thin plastic quad flatpack (TQFP). Pin Description A0–A14 CE CS0, CS1 OE GW BWE BW1–BW4 CLK ADV Address Inputs Chip Enable Chips Selects Output Enable Global Write Enable Byte Write Enable Individual Byte Write Selects Clock Input Burst Address Advance ADSC ADSP Address Status (Cache Controller) Address Status (Processor) LBO Linear / Interleaved Burst Order ZZ Sleep Mode I/O0–I/O31 Data Input/Output VDD, VDDQ Co re and I/O Power Supply (3.3V) VSS, VSSQ Array Ground, I/O Ground Input Input Input Input Input Input Input Input Input Input Input Input Input I/O Power Power Synchronous Synchronous Synchronous Asynchronous Synchronous Synchronous Synchronous N/A Synchronous Synchronous Synchronous DC Asynchronous Synchronous N/A N/A 3729 tbl 01 Pentium is a trademark of Intel Corp. PowerPC is a trademark of International Business Machines, Inc. ©2000 Integrated Device Technology, Inc. 1 AUGUST 2001 DSC-3729/04 1 page IDT71V433 32K x 32, 3.3V Synchronous SRAM with Flow-Through Outputs Pin Configuration Commercial and Industrial Temperature Ranges NC I/O16 I/O17 VDDQ VSSQ I/O18 I/O19 I/O20 I/O21 VSSQ VDDQ I/O22 I/O23 VSS(1) VDD NC VSS I/O24 I/O25 VDDQ VSSQ I/O26 I/O27 I/O28 I/O29 VSSQ VDDQ I/O30 I/O31 NC 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 1 80 2 79 3 78 4 77 5 76 6 75 7 74 8 73 9 72 10 71 11 70 12 69 13 68 14 67 15 PK100-1 66 16 65 17 64 18 63 19 62 20 61 21 60 22 59 23 58 24 57 25 56 26 55 27 54 28 53 29 52 30 51 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 NC I/O15 I/O14 VDDQ VSSQ I/O13 I/O12 I/O11 I/O10 VSSQ VDDQ I/O9 I/O8 VSS NC VDD ZZ(2) I/O7 I/O6 VDDQ VSSQ I/O5 I/O4 I/O3 I/O2 VSSQ VDDQ I/O1 I/O0 NC 3729 drw 02 Top View TQFP . NOTES 1. Pin 14 does not have to be directly connected to VSS as long as the input voltage is ≤ VIL. 2. Pin 64 can be left unconnected and the device will always remain in active mode. 6.452 5 Page IDT71V433 32K x 32, 3.3V Synchronous SRAM with Flow-Through Outputs Commercial and Industrial Temperature Ranges Timing Waveform of Combined Read and Write Cycles(1,2,3) . 6.1412 11 Page

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