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PDF LC66PG5XX Data sheet ( Hoja de datos )
| Número de pieza | LC66PG5XX | |
| Descripción | EPROM-Mountable Type 4-bit Microcomputer Evaluation Chip | |
| Fabricantes | Sanyo Semicon Device | |
| Logotipo |  |
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Ordering number:ENN2648
CMOS IC
LC66PG5XX
EPROM-Mountable Type 4-bit Microcomputer
Evaluation Chip for The LC665XX Series
Microcomputers
Overview
The LC66PG5XX is an EPROM-mountable type 4-bit mi-
crocomputer for developing and evaluating programs writ-
ten for the CMOS 4-bit single-chip LC665XX series mi-
crocomputers. Either 2764 or 27128 type EPROM can be
mounted on the LC66PG5XX. The LC66PG5XX with the
EPROM mounted can carry out the same functions as those
of the LC665XX series microcomputers. Therefore, you
can evaluate programs developed for application products
controlled by the LC665XX series microcomputers by in-
corporating the LC66PG5XX into the applications before
the programs are masked in the ROMs.
Pin assignment
Features
• Either 2764 or 27128 type EPROM can be mounted.
• Shrink type 64-pin configuration compatible with the
LC665XX series microcomputers. Note that pull-up re-
sistors need to be externally added.
• Options provided for selecting functions.
Options allowing the user to select output signal level for
ports 0, 1 and 8 at the initial reset or to specify whether
the watchdog timer function is employed by setting ex-
ternal pin levels
• Instruction cycle time 0.92 to 10 microseconds.
• +5V single power source.
The LC66PG5XX has the 28-pin soket and 14-pin soket
on the top face of the package. It also has the shrink type
64-pin terminals on the bottom face of the package. The
28-pin soket is used for mounting the EPROM containing
the programs and 14-pin soket for selecting functions by
options (input/output options not included). The shrink type
64-pin terminals are compatible with the LC665XX series
microcomputers.
Any and all SANYO products described or contained herein do not have specifications that can handle
applications that require extremely high levels of reliability, such as life-support systems, aircraft’s
control systems, or other applications whose failure can be reasonably expected to result in serious
physical and/or material damage. Consult with your SANYO representative nearest you before using
any SANYO products described or contained herein in such applications.
SANYO assumes no responsibility for equipment failures that result from using products at values that
exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges,or other
parameters) listed in products specifications of any and all SANYO products described or contained
herein.
SANYO Electric Co.,Ltd. Semiconductor Company
TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110-8534 JAPAN
N3001TN (KT)/7317KI, TS No.2648–1/14
1 page  
LC66PG5XX
Continued from preceding page
Terminal
name
Input/
output
Function
PC0
PC1
PC2/VREF0
PC3/VREF1
I/O Input/output port PC0 to PC3
•Data input and output in 4-bit units and in
1-bit units.
•PC2 also used as the VREF0 terminal for
reference voltage input.
•PC3 also used as the VREF1 terminal for
reference voltage input.
LC66PG5XX output
format
•Nch OD output
Option
(production chip)
•CMOS or Nch OD
output
At initial
reset
H
PD0/CMP0
PD1/CMP1
PD2/CMP2
PD3/CMP3
PE0/TRA
PE1/TRB
I Input port PD0 to PD3
•Can be selected as comparator input
terminals on programs.
PD0 : reference voltage input (VREF0).
PD1 to PD3 : reference voltage input
(VREF1)
•PD0, PD1 (PD2 to PD3) selectable as
comparator input ports on programs in this
unit.
I Input port
•Selectable as three-state input port on
programs.
–
–
– Normal input
– Normal input
OSC1
OSC2
I Terminals for system clock oscillator
O externally added.
•Leave OSC2 open and close OSC1 for
external clock signal input when external
clock mode is selected.
– •Ceramic resonator –
oscillation, RC (resistor
and capacitor) or
external clock selection.
RES
TEST
VDD
VSS
I Terminal for system reset signal input.
•CPU to be initialized when P33/HOLD="H"
plus "L" level voltage is applied to the RES
terminal.
I Terminal for CPU test signal input.
•Always connected to VSS during operation.
– Power source terminal
–
–
–
––
––
––
No.2648–5/14
5 Page 
LC66PG5XX
Continued from preceding page
Parameter
Symbol
Terminal
Data setup time
Data hold time
tICK
tCKI
SI0, SI1
Codnitions
VDD(V)
See Figure 5 "Serial
input/output timing"
Synchronized with the
rise (↑) of the SCK0
and SCK1 signals.
4.0 to 6.0
4.0 to 6.0
Output delay time tCKO
SO0, SO1
See Figure 5 "Serial
input/output timing"
and Figure 6 "Timing
load". Synchronized
with the fall (↓) of the
SCK0 and SCK1
signals.
4.0 to 6.0
INT0 high-level/
low-level/pulse
width
tI0H
tI0L
INT0
See •When INT0 interrupt
Figure is accepted.
7. •When timer 0 event
counter/pulse width
measure input is
accepted.
4.0 to 6.0
Interrupt input to
terminals other
than INT0. High-
level/low-level/
pulse width.
tI1H
tI1L
PIN1 high-level/
low-level/pulse
width
tPINH
tPINL
INT1, INT2
INT3, INT4
INT5
PIN1
•When each interrupt
is accepted.
•When timer 1 event
counter input is
accepted.
RES high-level/
low-level/pulse
width
tRSH
tRSL
RES
•When reset signai is
accepted.
Comparator response
speed
TRS
PD
See
Figure
8.
4.0 to 6.0
Operating mode current IDDop
drain
VDD
HALT mode current
drain
IDDHALT VDD
HOLD mode current
drain
IDDHOLD VDD
4MHz ceramic
resonator oscillation
4MHz external clock
RC oscillation
4MHz ceramic
resonator oscillation
4MHz external clock
RC oscillation
4.0 to 6.0
4.0 to 6.0
1.8 to 6.0
Ratings
min typ
0.3
0.3
max
Unit Note
µs
µs
0.3 µs
2 Tcyc
2 Tcyc
2 Tcyc
3 Tcyc
30 µs
4.5
6.5
4.0
1.0
2
1.2
0.01
8 mA
8
11
8
2.5 mA
9
3.5
2.5
10 µA
9
Note 1: Open drain output format and output Nch Tr OFF for input/output common ports.
Note 2: Open drain output format and output Nch Tr OFF for input/output common ports.
Note 6: Open drain output format and output Nch Tr OFF.
Note 7: Open drain output format and output Pch Tr OFF.
Note 8: Reset status. EPROM current drain not included.
Note 9: EPROM current drain not included.
No.2648–11/14
11 Page | ||
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