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PDF FS8170 Data sheet ( Hoja de datos )
| Número de pieza | FS8170 | |
| Descripción | Low Power Phase-locked Loop IC | |
| Fabricantes | Himark | |
| Logotipo |  |
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FS8170 2.5 GHz Low Power Phase-locked Loop IC
HiMARK Technology, Inc. reserves the right to change the product described in this datasheet. All information con-
tained in this datasheet is subject to change without prior notice. HiMARK Technology, Inc. assumes no responsibility
for the use of any circuits shown in this datasheet.
Description
The FS8170 IC is a serial data input, fully programmable phase-locked loop with a 2.5
GHz prescaler for use in the local oscillator subsystem of radio transceivers. Multi-modu-
lus division ratios of 32/33 and 64/65 are selectable thru serial programming to enable
pulse swallowing operation. When combined with an external VCO, the FS8170 becomes
the core of a very low power frequency synthesizer well-suited for mobile communication
applications, such as 2.4 GHz ISM-band wireless data links and cellular GSM and PCS.
The FS8170 is also pin compatible with Fujitsu’s MB15E07SL IC.
Features
! Maximum input frequency: 2.5 GHz
! Supply voltage range from 2.4 V to 3.6 V
! Low current consumption in locked state:
! Digitally-filtered lock detect output
3.5 mA typ. (VCC = VP = 2.7 V, TA = +25 °C)
4.0 mA typ. (VCC = VP = 3.0 V, TA= +25 °C)
10 µA max. in asynchronous power-down mode
! 18-bit programmable input frequency divider using ÷ 32/33/64/65 multi-modulus prescaler with divide ratio range
from 992 to 65631 for ÷ 32/33 mode and from 4032 to 131135 for ÷ 64/65 mode
! 14-bit programmable reference frequency divider with divide ratio range from 3 to 16383
! Programmable charge pump current: 1.5 mA or 6 mA
! Pin compatible with Fujitsu MB15E07, MB15E07L, MB15E07SL
! 16 pin, plastic TSSOP (0.65 mm pitch)
Package and Pin Assignment
16 pin, plastic TSSOP (dimensions in mm)
XIN 1
XOUT 2
VP 3
VCC 4
DO 5
VSS 6
XFIN 7
FIN 8
16 φR
15 φP
14 FOLD
13 ZC
12 EN
11 LE
10 DATA
9 CLK
Page 1
May 2003
1 page  
Electrical Characteristics
(VCC = VP = 3.0 V, VSS = 0 V, TA = –40 to 85 °C unless otherwise noted)
FS8170
Parameter
Symbol
Condition
Value
Unit
min. typ. max.
FOLD logic HIGH output voltage
FOLD logic LOW output voltage
FOLD logic HIGH output current
FOLD logic LOW output current
MICROWIRE TIMING
DATA to CLK setup time
DATA to CLK hold time
CLK to LE setup time
CLK to LE hold time
LE Pulse width
VOH
VCC = VP = 3.0 V, IOH = –1 mA
VCC –
0.4
VOL VCC = VP = 3.0 V, IOL = 1 mA
VOH VCC = VP = 3.0 V
VOL VCC = VP = 3.0 V 1
tSU1
tHOLD1
tSU2
tHOLD2
tEW
10
10
20
30
50
V
0.4 V
–1 mA
mA
ns
ns
ns
ns
ns
Page 5
May 2003
5 Page 
FS8170
Multi-function Lock Detect Output (FOLD)
A digital lock detect function is included with the phase detector through an internal digi-
tal filter to produce a logic level output which is available on the FOLD output pin. The
criterion of lock indication depends on the period of the crystal oscillator reference. The
lock dectect output is HIGH whenever the phase error between phase detector inputs is
less than 2 times of the crystal period for more than three consecutive comparison cycles,
otherwise is low. Note that LD becomes HIGH during the power saving mode. The LD
output is depicted in Fig. 3 as well.
Power-down Control (EN)
By setting the pin EN to LOW, the chip enters into power-down mode, reducing the cur-
rent consumption. During the power-down mode, the phase detector output, DO, is set to
its high impedance. Normal operation mode resumes when EN is switched to HIGH. To
prove a smooth start-up condition, an intermittent control circuit is activated when the
device returns to normal operation. Due to the unknown relationship between fV and fR
after returning from power-down, the PFD output is unpredictable and may give rise to a
significant jump in the VCO’s frequency which will result in an increased lock-up time.
To prevent this, the FS8170 employs an intermittent control circuit to limit the magnitude
of the error signal generated by the phase detector when it returns to normal operation,
thus ensuring a much quicker return to the fully phase-locked condition.
Table 8: Setting for the pin EN
EN Status
H Normal operation mode
L Power-down mode
Page 11
May 2003
11 Page | ||
| Páginas | Total 17 Páginas | |
| PDF Descargar | [ Datasheet FS8170.PDF ] | |
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