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PDF CDB5368 Data sheet ( Hoja de datos )
| Número de pieza | CDB5368 | |
| Descripción | 8-Channel A/D Converter | |
| Fabricantes | Cirrus Logic | |
| Logotipo |  |
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CS5368
114 dB, 192 kHz, 8-Channel A/D Converter
Overall Features
! Advanced Multi-bit Delta-Sigma Architecture
! 24-Bit Conversion
! 114 dB Dynamic Range
! -105 dB THD+N
! Supports Audio Sample Rates up to 216 kHz
! Selectable Audio Interface Formats
– Left-Justified, I²S, TDM
– 8-channel TDM Interface Formats
! Low Latency Digital Filter
! Less than 600 mW Power Consumption
! On-Chip Oscillator Driver
! Operation as System Clock Master or Slave
! Differential Analog Architecture
! Separate 1.8 V to 5 V Logic Supplie s for
Control and Serial Ports
! High-Pass Filter for DC Offset Calibration
! Overflow Detection
! Pin-Compatible with the 4-Channel CS5364
and 6-Channel CS5366
Additional Control Port Features
! Supports Standard I²C or SPI Control Interface
! Individual Channel HPF Disable
! Overflow Detection for Individual Channels
! Mute Control for Individual Channels
! Independent Power-Down Control per Channel
Pair
VA
5V
Internal
Osci l l ator
Voltage
Reference
VD
3.3 - 5V
Confi gurati on
Regi sters
Control Interface
I2C,SPI
or Pins
VLC
1.8 - 5V
Devi ce
Control
8 Differential
Analog Inputs
M ul ti -Bi t∆Σ
ADC
Deci m ati on
Fi l ter
High Pass
Fi l ter
Serial
Audio Out
PCMor
TDM
Di gi tal
Audio
VLS
1.8 - 5V
Advanced Product Information
http://www.cirrus.com
This document contains information for a new product.
Cirrus Logic reserves the right to modify this product without notice.
Copyright © Cirrus Logic, Inc. 2005
(All Rights Reserved)
JULY '05
DS624A1
1 page  
CS5368
LIST OF FIGURES
Figure 1. CS5368 Pinout................................................................................................................. 9
Figure 2. I²S/LJ Timing.................................................................................................................. 18
Figure 3. TDM Timing ................................................................................................................... 19
Figure 4. I²C Timing ...................................................................................................................... 20
Figure 5. SPI Timing ..................................................................................................................... 21
Figure 6. Typical Connection Diagram.......................................................................................... 23
Figure 7. Recommended Analog Input Buffer............................................................................... 24
Figure 8. Crystal Oscillator Topology ............................................................................................ 25
Figure 9. Master Slave Clock Flow ............................................................................................... 27
Figure 10. Master and Slave Clocking for a 32-Channel Application............................................ 27
Figure 11. Master Mode Clock Dividers ........................................................................................ 28
Figure 12. LJ Format..................................................................................................................... 30
Figure 13. I²S Format .................................................................................................................... 30
Figure 14. TDM Format................................................................................................................. 30
Figure 15. SPI Format................................................................................................................... 32
Figure 16. I²C Write Format ......................................................................................................... 33
Figure 17. I²C Read Format .......................................................................................................... 33
Figure 18. SSM Passband ............................................................................................................ 39
Figure 19. DSM Passband ............................................................................................................ 39
Figure 20. QSM Passband............................................................................................................ 39
Figure 21. SSM Stopband............................................................................................................. 40
Figure 22. DSM Stopband............................................................................................................. 40
Figure 23. QSM Stopband ............................................................................................................ 40
Figure 24. SSM -1 dB Cutoff ......................................................................................................... 41
Figure 25. DSM -1 dB Cutoff......................................................................................................... 41
Figure 26. QSM -1 dB Cutoff......................................................................................................... 41
DS624A1
5
5 Page 
CS5368
DC POWER CS5368
MCLK = 12.288 MHz; Master Mode. Power Down is defined as RST = LOW with all clocks and data lines held
static. GND = 0 V.
Parameter
Symbol Min Typ Max Unit
Power Supply Current
(Normal Operation)
VA = 5 V
VX = 5 V
VD = 5 V
VD = 3.3 V
VLS, VLC = 5 V
VLS, VLC = 3.3 V
Power Supply Current
(Power-Down)
VA = 5 V
VLS, VLC,VD = 5 V
Power Consumption
(Normal Operation)
All Supplies = 5 V
VA = 5 V, VD = VLS = VLC = 3.3 V
(Power-Down)
IA
IX
ID
ID
IL
IL
IA
ID
-
-
-
-
-
-
-
-
-
-
-
-
-
-
70 77 mA
4 8 mA
88 97 mA
58 64 mA
8 9 mA
5 6 mA
2 - mA
2 - mA
mW
830 915 mW
558 616 mW
35 - mW
LOGIC LEVELS
Parameter
Symbol Min Typ Max Units
High-Level Input Voltage
%VLS/VLC
VIH
70
-
-%
Low-Level Input Voltage
%VLS/VLC
VIL
- 30 %
High-Level Output Voltage at 100 µA load %VLS/VLC VOH
85
-
-%
Low-Level Output Voltage at -100 µA load %VLS/VLC VOL
-
- 15 %
OVFL Current Sink
-4 mA
Input Leakage Current
logic pins only
Iin
-
- ±10 µA
PSRR, VQ AND FILT+ CHARACTERISTICS
MCLK = 12.288 MHz; Master Mode. Valid with the recommended capacitor values on FILT+ and VQ as shown in
the “Typical Connection Diagram”.
Parameter
Power Supply Rejection Ratio at 1 kHz)
VQ Nominal Voltage
Output Impedance
Maximum allowable DC current source/sink
Filt+ Nominal Voltage
Output Impedance
Maximum allowable DC current source/sink
Symbol
PSRR
Min
-
-
-
-
-
-
-
Typ
65
VA/2
25
10
VA
4.4
10
Max Unit
- dB
-V
- kΩ
- µA
-V
- kΩ
- µA
14 DS624A1
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet CDB5368.PDF ] | |
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