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PDF IDT709199L Data sheet ( Hoja de datos )
| Número de pieza | IDT709199L | |
| Descripción | HIGH-SPEED 128K x 9 SYNCHRONOUS PIPELINED DUAL-PORT STATIC RAM | |
| Fabricantes | IDT | |
| Logotipo |  |
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HIGH-SPEED 128K x 9
SYNCHRONOUS PIPELINED
DUAL-PORT STATIC RAM
IDT709199L
Features
x True Dual-Ported memory cells which allow simultaneous
access of the same memory location
x High-speed clock to data access
– Commercial: 7.5/9/12ns (max.)
x Low-power operation
– IDT709199L
Active: 1.2W (typ.)
Standby: 2.5mW (typ.)
x Flow-Through or Pipelined output mode on either Port via
the FT/PIPE pins
x Counter enable and reset features
x Dual chip enables allow for depth expansion without
additional logic
x Full synchronous operation on both ports
– 4ns setup to clock and 0ns hold on all control, data, and
address inputs
– Data input, address, and control registers
– Fast 7.5ns clock to data out in the Pipelined output mode
– Self-timed write allows fast cycle time
– 12ns cycle time, 83MHz operation in Pipelined output mode
x TTL- compatible, single 5V (±10%) power supply
x Industrial temperature range (–40°C to +85°C) is
available for selected speeds
x Available in a 100-pin Thin Quad Flatpack (TQFP) package
Functional Block Diagram
R/WL
OEL
CE0L
CE1L
1
0
0/1
R/WR
OER
CE0R
1 CE1R
0
0/1
FT/PIPEL
I/O0L - I/O8L
0/1 1
0
I/O
Control
I/O
Control
0 1 0/1
A16L
A0L
CLKL
ADSL
CNTENL
CNTRSTL
Counter/
Address
Reg.
MEMORY
ARRAY
Counter/
Address
Reg.
FT/PIPER
I/O0R - I/O8R
A16R
A0R
CLKR
ADSR
CNTENR
CNTRSTR
4847 drw 01
©2000 Integrated Device Technology, Inc.
1
JANUARY 2001
DSC-4847/3
1 page  
IDT709199L
High-Speed 128K x 9 Synchronous Pipelined Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
DC Electrical Characteristics Over the Operating
Temperature and Supply Voltage Range(3,6) (VCC = 5V ± 10%)
709199L7
Com'l Only
709199L9
Com'l Only
709199L12
Com'l Only
Symbol
Parameter
Test Condition
Version
Typ.(4) Max. Typ.(4) Max. Typ.(4) Max. Unit
ICC Dynamic Operating
Current
(Both Ports Active)
CEL and CER= VIL
Outputs Disabled
f = fMAX(1)
COM'L L 275 465 250 400 230 355 mA
IND
L ____ ____ ____ ____ ____ ____
ISB1 Standby Current
(Both Ports - TTL
Level Inputs)
CEL = CER = VIH
f = fMAX(1)
COM'L
IND
L
L
95
____
150 80
____ ____
135 70
____ ____
110 mA
____
ISB2 Standby Current
(One Port - TTL
Level Inputs)
CE"A" = VIL and
CE"B" = VIH(3)
Active Port Outputs
Disabled, f=fMAX(1)
COM'L L 200 295 175 275 150 240 mA
IND
L ____ ____ ____ ____ ____ ____
ISB3 Full Standby Current
(Both Ports -
CMOS Level Inputs)
Both Ports CER and
CEL > VCC - 0.2V
VIN > VCC - 0.2V or
VIN < 0.2V, f = 0(2)
COM'L L 0.5 3 0.5 3 0.5 3 mA
IND
L ____ ____ ____ ____ ____ ____
ISB4 Full Standby Current
CE"A" < 0.2V and
COM'L L 190 290 170 270 140 225 mA
(One Port -
CE"B" > VCC - 0.2V(5)
CMOS Level Inputs)
VIN > VCC - 0.2V or
IND
L ____ ____ ____ ____ ____ ____
VIN < 0.2V, Active Port
Outp uts Disabled, f = fMAX(1)
NOTES:
4847 tbl 09
1. At f = fMAX, address and control lines (except Output Enable) are cycling at the maximum frequency clock cycle of 1/tCYC, using "AC TEST CONDITIONS" at input levels of
GND to 3V.
2. f = 0 means no address, clock, or control lines change. Applies only to input at CMOS level standby.
3. Port "A" may be either left or right port. Port "B" is the opposite from port "A".
4. Vcc = 5V, TA = 25°C for Typ, and are not production tested. ICC DC(f=0) = 150mA (Typ).
5. CEX = VIL means CE0X = VIL and CE1X = VIH
CEX = VIH means CE0X = VIH or CE1X = VIL
CEX < 0.2V means CE0X < 0.2V and CE1X > VCC - 0.2V
CEX > VCC - 0.2V means CE0X > VCC - 0.2V or CE1X < 0.2V
"X" represents "L" for left port or "R" for right port.
6. Industrial temperature: for specific speeds, packages and powers contact your sales office.
6.542
5 Page 
IDT709199L
High-Speed 128K x 9 Synchronous Pipelined Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Timing Waveform of Flow-Through Read-to-Write-to-Read (OE = VIL)(3)
tCYC1
tCH1
tCL1
CLK
CE0
CE1
R/W
tSC tHC
tSW tHW
tSW tHW
(4)
ADDRESS
An
tSA tHA
An +1
DATAIN
DATAOUT
(2)
tCD1
tCD1
Qn
READ
tDC
An + 2
An + 2
An + 3
An + 4
tSD tHD
Dn + 2
Qn + 1
tCKHZ(1)
NOP(5)
WRITE
tCD1
tCD1
Qn + 3
tCKLZ(1)
tDC
READ
4847 drw 13
Timing Waveform of Flow-Through Read-to-Write-to-Read (OE Controlled)(3)
tCYC1
tCH1
tCL1
CLK
CE0
CE1
R/W
tSC tHC
tSW tHW
tSW tHW
ADDRESS(4)
DATAIN
DATAOUT
An
tSA tHA
tCD1
(2)
An +1
An + 2
tSD tHD
Dn + 2
tDC
Qn
tOHZ (1)
An + 3
Dn + 3
An + 4
An + 5
tOE
tCD1
(1)
tCKLZ
tCD1
Qn + 4
tDC
OE
READ
WRITE
READ
4847 drw 14
NOTES:
1. Transition is measured 0mV from Low or High-impedance voltage with the Output Test Load (Figure 2).
2. Output state (High, Low, or High-impedance is determined by the previous cycle control signals.
3. CE0 and ADS = VIL; CE1, CNTEN, and CNTRST = VIH. "NOP" is "No Operation".
4. Addresses do not have to be accessed sequentially since ADS = VIL constantly loads the address on the rising edge of the CLK; numbers are for reference use only.
5. "NOP" is "No Operation." Data in memory at the selected address may be corrupted and should be re-written to guarantee data integrity.
61.412
11 Page | ||
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| PDF Descargar | [ Datasheet IDT709199L.PDF ] | |
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