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Triscend - (TA7S04 / TA7S20) Triscend A7S Configurable System-on-Chip Platform

Numéro de référence TA7S20
Description (TA7S04 / TA7S20) Triscend A7S Configurable System-on-Chip Platform
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TA7S20 fiche technique
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August, 2002 (Version 1.10)
®
! Industry’s first complete 32-bit Configurable
System-on-Chip (CSoC)
High-performance, low-power consumption,
32-bit RISC processor (ARM7TDMI™)
8Kbyte mixed instruction/data cache
16Kbyte internal scratchpad RAM
Next-generation embedded programmable
logic architecture (up to 25,600 ASIC gates)
High-performance dedicated internal bus
(up to 455Mbytes per second at 60 MHz)
External memory interface supporting
Flash, EEPROM, SRAM, and SDRAM
Advanced real-time, in-system debugging
capability
Stand-alone operation from a single
external memory (code + initialization)
2.5-volt core with 3.3- or 2.5-volt I/Os
Four independent high-performance DMA
channels
Triscend A7S Configurable
System-on-Chip Platform
Product Description
! High-performance, 32-bit
ARM7TDMI RISC Processor
Popular, industry-standard 32-
bit RISC processor
Binary and source code
compatible with other ARM7/ARM7TDMI
variants
Widespread C/C++ compiler, source-level
debugger, and RTOS support
Superior code density using the Thumb®
instruction set
54 MIPS (Dhrystone 2.1) at 60 MHz
Low latency, real-time interrupt response
Fast hardware multiplier
32-bit register bank and ALU
32-bit addressing 4Gbyte linear address
32-bit barrel shifter
EmbeddedICE™ on-chip debugger
To external memory
?
Clock Synthesizer
Power Control
Power-On Reset
Memory Interface
Unit
SDRAM Controller
Static/Flash Interface
ARM7TDMI
16KBytes
ScratchPad
SRAM
or
Trace Buffer
Cache
* 8K Bytes
* 4-way Set Associative
* Protection Unit
CSI Bridge
CSI Bus
Arbiter
Hardware
Breakpoint Unit
Four-channel
DMA Controller
JTAG Interface
Selector
Selector
Selector
Selector
Selector
Selector
Configurable
System Logic
(CSL)
matrix
PIO
PIO
PIO
PIO
PIO
PIO
PIO
PIO
Configurable System
Interconnect socket
Standard Peripherals
16-input
Interrupt Controller
16-bit
Timer
16-bit
Timer
32-bit
Watchdog Timer
UART
UART
with FIFO with FIFO
Configurable System
Interconnect (CSI) bus
Figure 1. Block diagram of the Triscend A7S Configurable System-on-Chip (CSoC).
© 2000-2002 by Triscend Corporation. All rights reserved.
Patents Pending.
TCH305-0001-002

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