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PDF TA7S04 Data sheet ( Hoja de datos )
| Número de pieza | TA7S04 | |
| Descripción | (TA7S04 / TA7S20) Triscend A7S Configurable System-on-Chip Platform | |
| Fabricantes | Triscend | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de TA7S04 (archivo pdf) en la parte inferior de esta página. Total 30 Páginas | ||
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August, 2002 (Version 1.10)
®
! Industry’s first complete 32-bit Configurable
System-on-Chip (CSoC)
• High-performance, low-power consumption,
32-bit RISC processor (ARM7TDMI™)
• 8Kbyte mixed instruction/data cache
• 16Kbyte internal scratchpad RAM
• Next-generation embedded programmable
logic architecture (up to 25,600 ASIC gates)
• High-performance dedicated internal bus
(up to 455Mbytes per second at 60 MHz)
• External memory interface supporting
Flash, EEPROM, SRAM, and SDRAM
• Advanced real-time, in-system debugging
capability
• Stand-alone operation from a single
external memory (code + initialization)
• 2.5-volt core with 3.3- or 2.5-volt I/Os
• Four independent high-performance DMA
channels
Triscend A7S Configurable
System-on-Chip Platform
Product Description
! High-performance, 32-bit
ARM7TDMI RISC Processor
• Popular, industry-standard 32-
bit RISC processor
• Binary and source code
compatible with other ARM7/ARM7TDMI
variants
• Widespread C/C++ compiler, source-level
debugger, and RTOS support
• Superior code density using the Thumb®
instruction set
• 54 MIPS (Dhrystone 2.1) at 60 MHz
• Low latency, real-time interrupt response
• Fast hardware multiplier
• 32-bit register bank and ALU
• 32-bit addressing ― 4Gbyte linear address
• 32-bit barrel shifter
• EmbeddedICE™ on-chip debugger
To external memory
?
Clock Synthesizer
Power Control
Power-On Reset
Memory Interface
Unit
SDRAM Controller
Static/Flash Interface
ARM7TDMI
16KBytes
ScratchPad
SRAM
or
Trace Buffer
Cache
* 8K Bytes
* 4-way Set Associative
* Protection Unit
CSI Bridge
CSI Bus
Arbiter
Hardware
Breakpoint Unit
Four-channel
DMA Controller
JTAG Interface
Selector
Selector
Selector
Selector
Selector
Selector
Configurable
System Logic
(CSL)
matrix
PIO
PIO
PIO
PIO
PIO
PIO
PIO
PIO
Configurable System
Interconnect socket
Standard Peripherals
16-input
Interrupt Controller
16-bit
Timer
16-bit
Timer
32-bit
Watchdog Timer
UART
UART
with FIFO with FIFO
Configurable System
Interconnect (CSI) bus
Figure 1. Block diagram of the Triscend A7S Configurable System-on-Chip (CSoC).
© 2000-2002 by Triscend Corporation. All rights reserved.
Patents Pending.
TCH305-0001-002
1 page  
Four-Channel DMA
The four-channel DMA controller provides high-bandwidth communication between CSL-
based I/O devices, at up to 228M bytes per second, per direction. The easy-to-use DMA
handshake simplifies interface and control logic within the CSL. The DMA controller pro-
vides advanced capabilities such as linked-list and frame-transfer support.
Dedicated Peripherals
The A7S also offers a set of common dedicated peripherals including
# two 16-bit timers with pre-scalers,
# two 16C450/550-like serial controllers (UART), with an optional modem interface
# a 32-bit watchdog timer, and
# an interrupt controller.
Complete Single-Chip System
The majority of the system, including the CPU, operates from a single clock signal. The
clock source is typically driven directly via an external pin or connected to the on-chip PLL
clock synthesizer. The clock synthesizer operates from an external 32.768 kHz watch
crystal. Additionally, an internal ring oscillator is provided. Six other global buffers pro-
vide high-fanout signals to CSL functions. The bus clock and the global buffers are op-
tionally stopped upon a breakpoint event and shut off during power-down mode.
Power management controls provide selectable power-down options over internal func-
tions. Furthermore, each PIO provides pin-by-pin power-down settings.
An internal initialization boot ROM controls device initialization after power-on or after the
reset pin is released. The initialization boot ROM locates user's initialization data and
code stored in external Flash or other non-volatile memory. The Triscend FastChip de-
velopment system programs external Flash via the A7S’s JTAG port.
Additionally, the JTAG interface provides real-time, in-system debugging capabilities,
eliminating the need for an external emulator. The JTAG interface has full access and
control over the CPU, peripherals, and CSL functions during debugging.
When debugging application software, the A7S employs the rich set of standard
ARM7TDMI debugging tools. The A7S fully supports the standard ARM internal break-
point and watchpoint capabilities. In addition, the A7S’s breakpoint unit monitors both the
CPU local bus or the CSI bus. Upon a predefined set of conditions, the breakpoint unit
halts or interrupts the execution of the application program. The breakpoint unit also sup-
ports real-time tracing of local CPU bus or the CSI bus transactions.
All together, the Triscend A7S Configurable System-on-Chip (CSoC) platform offers un-
paralleled time-to-market and performance advantages for embedded system designs.
TCH305-0001-002
5 SUBJECT TO CHANGE
5 Page 
Arithmetic Logic Unit
The arithmetic logic unit (ALU) performs 32-bit arithmetic and logic instructions in a single
clock cycle.
Barrel Shifter
The 32-bit barrel shifter allows a general shift operation to be combined with a general
ALU operation in a single instruction that executes in a single clock cycle.
Hardware Multiplier
The ARM7TDMI processor includes a dedicated 32 x 8 hardware multiplier. Additionally,
the multiplier supports multiply-accumulate functions, which are central to many digital
signal processing (DSP) applications.
The performance of the multiplier depends on the data values and the type of data multi-
plied, as shown in Table 4. The multiplier terminates the instruction immediately upon
computing the result, regardless of the data width.
Table 4. ARM7TDMI Multiplier Performance.
Multiplier Operation
32 x 32 = 32
Multiply two 32-bit values with a 32-bit result
32 x 32 = 64
Multiply two 32-bit values with a 64-bit result
32 x 32 + 32 = 32
Multiply two 32-bit values, add the result with a 32-bit value, producing
a 32-bit result
32 x 32 + 64 = 64
Multiply two 32-bit values, add the result with a 64-bit value, producing
a 64-bit result
Clock Cycles
2 to 5
3 to 6
3 to 6
4 to 7
Conditional Code Execution
Each ARM instruction is conditionally executed, based on the current status flags. The
capability minimizes short branches, which might otherwise reduce system performance.
Three-Address Data Processing Instructions
The two source operand registers and the result register are independently specified,
which aids performance and improves code density.
Thumb Instruction Set
The Thumb instruction set provides an extremely dense 16-bit representation of the most
commonly used instructions. Thumb offers cost advantages for smaller systems and per-
formance advantages in systems with 8-bit or 16-bit external memory subsystems.
CISC-like Instructions
Load and store multiple instructs allow an application to quickly and easily save and re-
store registers
TCH305-0001-002
11 SUBJECT TO CHANGE
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet TA7S04.PDF ] | |
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