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PDF ICS553 Data sheet ( Hoja de datos )
| Número de pieza | ICS553 | |
| Descripción | LOW SKEW 1 TO 4 CLOCK BUFFER | |
| Fabricantes | ICST | |
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ICS553
LOW SKEW 1 TO 4 CLOCK BUFFER
Description
The ICS553 is a low skew, single input to four output,
clock buffer. Part of ICS’ Clock BlocksTM family, this is
our lowest skew, small clock buffer. See the ICS552-02
for a 1 to 8 low skew buffer. For more than 8 outputs
see the MK74CBxxx BuffaloTM series of clock drivers.
ICS makes many non-PLL and PLL based low skew
output devices as well as Zero Delay Buffers to
synchronize clocks. Contact us for all of your clocking
needs.
Features
• Extremely low skew outputs (50ps maximum)
• Packaged in 8 pin SOIC
• Low power CMOS technology
• Operating Voltages of 2.5 to 5V
• Output Enable pin tri-states outputs
• 5V tolerant input clock
Block Diagram
ICLK
Q0
Q1
Q2
Q3
Output Enable
MDS 553 B
1
Revision 052501
Integrated Circuit Systems q 525 Race Street, San Jose, CA 95126 q tel (408) 295-9800 q www.icst.com
1 page  
ICS553
LOW SKEW 1 TO 4 CLOCK BUFFER
AC Electrical Characteristics
VDD = 2.5V ±5%, Ambient Temperature 0 to +70° C, unless stated otherwise
Parameter
Symbol
Conditions
Min. Typ.
Input Frequency
0
Output Rise Time
Output Fall Time
Propagation Delay
tOR
tOF
Note 1
0.8 to 2.0V, CL=15pF
2.0 to 0.8V, CL=15pF
3
Output to output skew
Note 2 Rising edges at VDD/2
0
Max.
200
1.5
1.5
50
Units
MHz
ns
ns
ns
ps
VDD = 3.3V ±5%, Ambient Temperature 0 to +70° C, unless stated otherwise
Parameter
Symbol
Conditions
Min. Typ.
Input Frequency
0
Output Rise Time
Output Fall Time
Propagation Delay
tOR
tOF
Note 1
0.8 to 2.0V, CL=15pF
2.0 to 0.8V, CL=15pF
2.6
Output to output skew
Note 2 Rising edges at VDD/2
0
Max.
200
1.0
1.0
50
Units
MHz
ns
ns
ns
ps
VDD = 5V ±5%, Ambient Temperature 0 to +70° C, unless stated otherwise
Parameter
Symbol
Conditions
Min. Typ. Max. Units
Input Frequency
0 200 MHz
Output Rise Time
Output Fall Time
Propagation Delay
tOR
tOF
Note 1
0.8 to 2.0V, CL=15pF
2.0 to 0.8V, CL=15pF
0.7
0.7
2.5
ns
ns
ns
Output to output skew
Note 2 Rising edges at VDD/2
0 50 ps
Notes: 1. With rail to rail input clock
2. Between any 2 outputs with equal loading.
3. Duty cycle on outputs will match incoming clock duty cycle. Consult ICS for tight duty cycle clock
generators.
MDS 553 B
5
Revision 052501
Integrated Circuit Systems q 525 Race Street, San Jose, CA 95126 q tel (408) 295-9800 q www.icst.com
5 Page | ||
| Páginas | Total 6 Páginas | |
| PDF Descargar | [ Datasheet ICS553.PDF ] | |
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