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PDF ICS552-03 Data sheet ( Hoja de datos )
| Número de pieza | ICS552-03 | |
| Descripción | LOW SKEW 1 TO 8 CLOCK BUFFER | |
| Fabricantes | ICST | |
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ICS552-03
LOW SKEW 1 TO 8 CLOCK BUFFER (4 AT 1X, 4 AT 1/2X)
Description
The ICS552-03 is a low skew, single input to eight
output clock buffer. Four of the outputs are exact copies
of the input, while the other four are divide by 2 copies
of the input. It is part of ICS’ Clock BlocksTM family. See
the ICS553 for a 1 to 4 low skew buffer, or the
ICS552-02 for a 1 to 8 low skew buffer without divide by
2. For more than 8 outputs see the MK74CBxxx
BuffaloTM series of clock drivers.
ICS makes many non-PLL and PLL based low skew
output devices as well as Zero Delay Buffers to
synchronize clocks. Contact us for all of your clocking
needs.
Features
• Low skew outputs (50 ps maximum)
• Packaged in 16 pin TSSOP
• Low power CMOS technology
• Operating Voltages of 2.5 V to 5 V
• Output Enable pin tri-states outputs
• Low skew between 1X and 1/2X outputs (100 ps
maximum)
• One bank of 4 outputs at 1X
• One bank of 4 outputs at 1/2X
• 5V tolerant input clocks
• Input clock multiplexer
Block Diagram
INA 1
INB 0
D iv id e
by 2
Q0
Q1
Q2
Q3
P0
P1
P2
P3
SELA
OE
MDS 552-03 B
1
Revision 052501
Integrated Circuit Systems q 525 Race Street, San Jose, CA 95126 q tel (408) 295-9800 q www.icst.com
1 page  
ICS552-03
LOW SKEW 1 TO 8 CLOCK BUFFER (4 AT 1X, 4 AT 1/2X)
AC Electrical Characteristics (continued)
VDD = 3.3V ±5%, Ambient Temperature 0 to +70° C, unless stated otherwise
Parameter
Symbol
Conditions
Min. Typ.
Input Frequency
0
Output Rise Time
Output Fall Time
Propagation Delay
tOR
tOF
Note 1
0.8 to 2.0 V, CL=15 pF
2.0 to 0.8 V, CL=15 pF
1.0
1.0
5
Output to output skew. Between Note 2 Rising edges at VDD/2
any two Q outputs
0
Output to output skew. Between Note 2 Rising edges at VDD/2
any two P outputs
0
Output to output skew. Between Note 2 Rising edges at VDD/2
any P to any Q output
0
Input A to Input B skew
Note 3
0
Max.
200
50
50
100
50
Units
MHz
ns
ns
ns
ps
ps
ps
ps
VDD = 5.0V ±5%, Ambient Temperature 0 to +70° C, unless stated otherwise
Parameter
Symbol
Conditions
Min. Typ. Max. Units
Input Frequency
0 160 MHz
Output Rise Time
Output Fall Time
Propagation Delay
tOR
tOF
Note 1
0.8 to 2.0 V, CL=15 pF
2.0 to 0.8 V, CL=15 pF
0.7 ns
0.7 ns
4 ns
Output to output skew. Between Note 2 Rising edges at VDD/2
any two Q outputs
0 50 ps
Output to output skew. Between Note 2 Rising edges at VDD/2
any two P outputs
0 50 ps
Output to output skew. Between Note 2 Rising edges at VDD/2
any P to any Q output
0 100 ps
Input A to Input B skew
Note 3
0 50 ps
Notes: 1. With rail to rail input clock
2. Between any two outputs with equal loading
3. Propagation delay matching through the part
4. Duty cycle on outputs will match incoming clock duty cycle. Consult ICS for tight duty cycle clock
generators.
MDS 552-03 B
5
Revision 052501
Integrated Circuit Systems q 525 Race Street, San Jose, CA 95126 q tel (408) 295-9800 q www.icst.com
5 Page | ||
| Páginas | Total 6 Páginas | |
| PDF Descargar | [ Datasheet ICS552-03.PDF ] | |
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