|
|
PDF ICS552-02 Data sheet ( Hoja de datos )
| Número de pieza | ICS552-02 | |
| Descripción | LOW SKEW 2 INPUT MUX AND 1 TO 8 CLOCK BUFFER | |
| Fabricantes | ICST | |
| Logotipo |  |
|
Hay una vista previa y un enlace de descarga de ICS552-02 (archivo pdf) en la parte inferior de esta página. Total 6 Páginas | ||
|
No Preview Available !
www.DataSheet4U.com
ICS552-02
LOW SKEW 2 INPUT MUX AND 1 TO 8 CLOCK BUFFER
Description
The ICS552-02 is a low skew, single-input to eight-
output clock buffer. It is part of ICS’ Clock BlocksTM
family. See the ICS553 for a 1 to 4 low skew buffer. For
more than 8 outputs see the MK74CBxxx BuffaloTM
series of clock drivers.
ICS makes many non-PLL and PLL based low skew
output devices as well as Zero Delay Buffers to
synchronize clocks. Contact us for all of your clocking
needs.
Features
• Extremely low skew outputs (50ps maximum)
• Packaged in 16 pin TSSOP
• Low power CMOS technology
• Operating Voltages of 2.5 V to 5 V
• Output Enable pin tri-states outputs
• 5 V tolerant input clocks
• Input/Output clock frequency up to 200 MHz
• Input clock multiplexer simplifies clock selection
Block Diagram
INA 1
INB 0
SELA
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
OE
MDS 552-02 B
1
Revision 050401
Integrated Circuit Systems q 525 Race Street, San Jose, CA 95126 q tel (408) 295-9800 q www.icst.com
1 page  
PRELIMINARY INFORMATION
ICS552-02
LOW SKEW 2 INPUT MUX AND 1 TO 8 CLOCK
AC Electrical Characteristics
VDD = 2.5V ±5%, Ambient Temperature 0 to +70° C, unless stated otherwise
Parameter
Symbol
Conditions
Min. Typ.
Input Frequency
0
Output Rise Time
Output Fall Time
Propagation Delay
tOR
tOF
Note 1
0.8 to 2.0 V, CL=15 pF
2.0 to 0.8 V, CL=15 pF
1.5
1.5
3.5
Output to output skew
Note 2 Rising edges at VDD/2
0
Input A to Input B skew
Note 3
0
Max.
200
50
50
Units
MHz
ns
ns
ns
ps
ps
VDD = 3.3V ±5%, Ambient Temperature 0 to +70° C, unless stated otherwise
Parameter
Symbol
Conditions
Min. Typ.
Input Frequency
0
Output Rise Time
Output Fall Time
Propagation Delay
tOR
tOF
Note 1
0.8 to 2.0 V, CL=15 pF
2.0 to 0.8 V, CL=15 pF
1.0
1.0
3.0
Output to output skew
Note 2 Rising edges at VDD/2
0
Input A to Input B skew
Note 3
0
Max.
200
50
50
Units
MHz
ns
ns
ns
ps
ps
VDD = 5.0V ±5%, Ambient Temperature 0 to +70° C, unless stated otherwise
Parameter
Symbol
Conditions
Min. Typ.
Input Frequency
0
Output Rise Time
Output Fall Time
Propagation Delay
tOR
tOF
Note 1
0.8 to 2.0 V, CL=15 pF
2.0 to 0.8 V, CL=15 pF
0.7
0.7
2.8
Output to output skew
Note 2 Rising edges at VDD/2
0
Input A to Input B skew
Note 3
0
Max.
200
50
50
Units
MHz
ns
ns
ns
ps
ps
Notes: 1. With rail-to-rail input clock.
2. Between any two outputs with equal loading.
3. Propagation delay matching through the part.
4. Duty cycle on outputs will match incoming clock duty cycle. Consult ICS for tight duty cycle clock
generators.
MDS 552-02 B
5
Revision 050401
Integrated Circuit Systems q 525 Race Street, San Jose, CA 95126 q tel (408) 295-9800 q www.icst.com
5 Page | ||
| Páginas | Total 6 Páginas | |
| PDF Descargar | [ Datasheet ICS552-02.PDF ] | |
Hoja de datos destacado
| Número de pieza | Descripción | Fabricantes |
| ICS552-01A | Crystal Oscillator & Multiplier | ICST |
| ICS552-02 | LOW SKEW 2 INPUT MUX AND 1 TO 8 CLOCK BUFFER | ICST |
| ICS552-03 | LOW SKEW 1 TO 8 CLOCK BUFFER | ICST |
| Número de pieza | Descripción | Fabricantes |
| SLA6805M | High Voltage 3 phase Motor Driver IC. |
 Sanken |
| SDC1742 | 12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters. |
 Analog Devices |
|
DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares, |
| DataSheet.es | 2020 | Privacy Policy | Contacto | Buscar |