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PDF HMU17 Data sheet ( Hoja de datos )
| Número de pieza | HMU17 | |
| Descripción | (HMU16 / HMU17) 16 x 16-Bit CMOS Parallel Multipliers | |
| Fabricantes | Intersil Corporation | |
| Logotipo |  |
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TM
Data Sheet
HMU16, HMU17
November 1999
File Number 2803.4
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16 x 16-Bit CMOS Parallel Multipliers
The HMU16 and HMU17 are high speed, low power CMOS
16-bit x 16-bit multipliers ideal for fast, real time digital signal
processing applications.
The X and Y operands along with their mode controls (TCX
and TCY) have 17-bit input registers. The mode controls
independently specify the operands as either two’s
complement or unsigned magnitude format, thereby allowing
mixed mode multiplication operations.
Two 16-bit output registers are provided to hold the most and
least significant halves of the result (MSP and LSP). For
asynchronous output, these registers may be made
transparent through the use of the Feedthrough Control
(FT).
Additional inputs are provided for format adjustment and
rounding. The Format Adjust control (FA) allows the user to
select either a left shifted 31-bit product or a full 32-bit
product, whereas the round control (RND) provides the
capability of rounding the most significant portion of the
result.
The HMU16 has independent clocks (CLKX, CLKY, CLKL,
CLKM) associated with each of these registers to maximize
throughput and simplify bus interfacing. The HMU17 has
only a single clock input (CLK), but makes use of three
register enables (ENX, ENY and ENP). The ENX and ENY
inputs control the X and Y Input Registers, while ENP
controls both the MSP and LSP Output Registers. This
configuration facilitates the use of the HMU17 for
microprogrammed systems.
The two halves of the product may be routed to a single
16-bit three-state output port via a multiplexer, and in
addition, the LSP is connected to the Y-input port through a
separate three-state buffer.
Features
• 16 x 16-Bit Parallel Multiplier with Full 32-Bit Product
• High-Speed (35ns) Clocked Multiply Time
• Low Power Operation
- ICCSB = 500µA Maximum
- ICCOP = 7.0mA Maximum at 1MHz
• Supports Two’s Complement, Unsigned Magnitude and
Mixed Mode Multiplication
• HMU16 is Compatible with the AM29516, LMU16,
IDT7216 and the CY7C516
• HMU17 is Compatible with the AM29517, LMU17,
IDT7217 and the CY7C517
• TTL Compatible Inputs/Outputs
• Three-State Outputs
Applications
• Fast Fourier Transform Analysis
• Digital Filtering
• Graphic Display Systems
• Image Processing
• Radar and Sonar
• Speech Synthesis and Recognition
Ordering Information
PART NUMBER
HMU16JC-35
HMU16JC-45
TEMP.
RANGE (oC)
PACKAGE
0 to 70 68 Ld PLCC
0 to 70 68 Ld PLCC
HMU16GC-35
HMU16GC-45
HMU17JC-35
HMU17JC-45
0 to 70
0 to 70
0 to 70
0 to 70
68 Ld CPGA
68 Ld CPGA
68 Ld PLCC
68 Ld PLCC
HMU17GC-35
HMU17GC-45
0 to 70
0 to 70
68 Ld CPGA
68 Ld CPGA
PKG.
NO.
N68.95
N68.95
G68.B
G68.B
N68.95
N68.95
G68.B
G68.B
1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Intersil and Design is a trademark of Intersil Americas Inc.
Copyright © Intersil Americas Inc. 2001, All Rights Reserved
1 page  
HMU16, HMU17
Functional Description
The HMU16/HMU17 are high speed 16 x 16-bit multipliers
designed to perform very fast multiplication of two 16-bit
binary numbers. The two 16-bit operands (X and Y) may be
independently specified as either two's complement or
unsigned magnitude format by the two's complement
controls (TCX and TCY). When either of these control lines
is LOW, the respective operand is treated as an unsigned
16-bit value; and when it is HIGH, the operand is treated as
a signed value represented in two's complement format. The
operands along with their respective controls are latched at
the rising edge of the associated clock signal. The HMU16
accomplishes this through the use of independent clock
inputs for each of the Input Registers (CLKX and CLKY),
while the HMU17 utilizes a single clock signal (CLK) along
with the X and Y register enable inputs (ENX and ENY).
Input controls are also provided for rounding and format
adjustment of the 32-bit product. The Round input (RND) is
provided to accommodate rounding of the most significant
portion of the product by adding one to the Most Significant
Bit (MSB) of the LSP Register. The position of the MSB is
dependent on the state of the Format Adjust Control (see Pin
Descriptions and Multiplier Input/Output Format Tables). The
Round input is latched into the RND Register whenever
either of the input registers is clocked. The Format Adjust
control (FA) allows the product output to be formatted. When
the FA control is HIGH, a full 32-bit product is output; and
when FA is LOW, a left-shifted 31-bit product is output with
the sign bit replicated in bit position 15 of the LSP. The FA
control must be HIGH for unsigned magnitude, and mixed
mode multiplication operations. It may be LOW for certain
two's complement integer and fractional operations only (see
Multiplier Input/ Output Formats Table).
The HMU16/HMU17 multipliers are equipped with two 16-bit
Output Registers (MSP and LSP) which are provided to hold
the most and least significant portions of the resultant
product respectively. The HMU16 uses independent clocks
(CLKM and CLKL) for latching the two output registers, while
the HMU17 uses a single clock input (CLK) along with the
Product Latch Enable (ENP). The MSP and LSP Registers
may also be made transparent for asynchronous output
through the use of the Feed through Control (FT). There are
two output configurations which may be selected when using
the HMU16/HMU17 multipliers. The first configuration allows
the simultaneous access of the most and least significant
halves of the product. When the MSPSEL input is LOW, the
Most Significant Product will be available at the dedicated
output port (P16-31/P0-15). The Least Significant Product is
simultaneously available at the bidirectional port shared with
the Y-inputs (Y0-15/P0-15) through the use of the LSP
output enable (OEL). The other output configuration involves
multiplexing the MSP and LSP Registers onto the dedicated
output port through the use of the MSPSEL control. When
the MSPSEL control is LOW, the Most Significant Product
will be available at the dedicated output port; and when
MSPSEL is HIGH, the Least Significant Product will be
available at this port. This configuration allows access of the
entire 32-bit product by a 16-bit wide system bus.
5
5 Page 
HMU16, HMU17
Timing Diagrams
DATA
INPUT
CLOCK
INPUT
tS tH
FIGURE 7. SETUP AND HOLD TIME
3.0V
1.5V
0V
3.0V
1.5V
0V
CLKX
CLKY
INPUT
XI YI
RND
CLKM
CLKL
OUTPUT Y
tS
MSPSEL
OUTPUT P
tPWH
tH
tMC
tHCL
tPWL
tPDY
tPDSEL
tPDP
tMUC
FIGURE 9. HMU16 TIMING DIAGRAM
THREE
STATE
CONTROL
1.5V
tDIS tENA
OUTPUT
THREE
STATE
HIGH IMPEDANCE
1.7V
1.3V
FIGURE 8. THREE-STATE CONTROL
tPWH
CLK
ENX
ENY
INPUT
XI YI
RND
ENP
OUTPUT Y
MSPSEL
OUTPUT P
tSE
tS
tHE
tH
tPWL
tSE
tMC
tPDSEL
tPDP
tMUC
tHE
tPDY
FIGURE 10. HMU17 TIMING DIAGRAM
11
11 Page | ||
| Páginas | Total 13 Páginas | |
| PDF Descargar | [ Datasheet HMU17.PDF ] | |
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