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PDF CDB53L32A Data sheet ( Hoja de datos )
| Número de pieza | CDB53L32A | |
| Descripción | Stereo A/D Converter | |
| Fabricantes | Cirrus Logic | |
| Logotipo |  |
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CS53L32A
Low Voltage, Stereo A/D Converter
FEATURES
z 20-Pin TSSOP package
z 1.8 V to 3.3 V supply
z 24-bit conversion / 96 kHz sample rate
z 98 dB dynamic range at 3 V supply
z -88 dBFS THD+N
z Low power consumption
– 11 mW at 1.8 V
z Up to 32 dB gain
– 20 dB gain step
– 12 dB variable input gain, 1 dB steps
– Changes made at zero crossings
z Stereo inputs
z Digital volume control
– 96 dB attenuation, 1 dB step size
– Mute
– Soft ramping
z 2:1 Input mux
II
DESCRIPTION
The CS53L32A is a highly integrated, 24-bit, 96 kHz au-
dio ADC providing stereo analog-to-digital converters
using delta-sigma conversion techniques. This device in-
cludes volume control and line level inputs in a 20-pin
TSSOP package.
The CS53L32A is based on delta-sigma modulation al-
lowing infinite adjustment of the sample rate between
2 kHz and 100 kHz simply by changing the master clock
frequency.
The CS53L32A contains adjustable analog gain, a 2:1
input mux, and digital attenuation.
The CS53L32A operates from a +1.8 V to +3.3 V supply.
These features are ideal for portable MP3 players, MD
recorders/players, digital camcorders, PDAs, set-top
boxes, and other portable systems that require extreme-
ly low power consumption in a minimum of space.
ORDERING INFORMATION
CS53L32A-KZ 20-pin TSSOP -10 to 70 °C
CS53L32A-KZZ 20-pin TSSOP -10 to 70 °C
CS53L32A-BZ 20-pin TSSOP -40 to 85 °C
CDB53L32A
Evaluation Board
Lead free
RST
VA
VL
LRCK
SCLK
SDOUT
SCL/CCLK/ChSEL SDA/CDIN/DIF AD0/CS/DIV
Attenuator
0-96 dB
Attenuator
0-96 dB
GND VQ
Control Port
Digital
Filters
ADC
ADC
MCLK FILT+ REF_GND
Gain
Gain
AFLTL
AFLTR
AIN_L1
AIN_L2
AIN_R1
AIN_R2
http://www.cirrus.com
Copyright © Cirrus Logic, Inc. 2004
(All Rights Reserved)
OCT ‘04
DS513F1
1 page  
CS53L32A
ANALOG CHARACTERISTICS (CONTINUED)
Base-rate Mode
Parameter
Symbol Min Typ Max
Total Harmonic Distortion + Noise (PGA on)*
THD+N
(Note 1)
0 dB Gain
18 to 24-Bit
-1 dB
- 78 -
12 dB Gain
18 to 24-Bit
-1 dB
- 73 -
CS53L32A-KZ/KZZ Analog Input Characteristics for VA=1.8 V - 3.3 V
Interchannel Isolation
1 kHz
- 90 -
Interchannel Gain Mismatch
- 0.1 -
Offset Error
with High Pass Filter
- -0
Full Scale Input Voltage
-5% VA/3.6 +5%
Gain Drift
- 100 -
Input Resistance
10 -
-
Input Capacitance
- - 15
CS53L32A-BZ Analog Input Characteristics for VA = 1.8 V
Dynamic Range
A-weighted
unweighted
86 93
83 90
-
-
Total Harmonic Distortion + Noise
18 to 24-Bit
16-Bit
(Note 1) THD+N
-1 dB
-20 dB
-60 dB
-1 dB
-20 dB
-60 dB
-
-
-
-
-
-
-88 -81
-70 -
-30 -
-86 -
-68 -
-28 -
Dynamic Range (PGA on)*
0 dB Gain
A-weighted
unweighted
12 dB Gain
A-weighted
unweighted
- 90 -
- 87 -
- 85 -
- 82 -
Total Harmonic Distortion + Noise (PGA on)*
THD+N
(Note 1)
0 dB Gain
18 to 24-Bit
-1 dB
- 85 -
12 dB Gain
18 to 24-Bit
-1 dB
- 83 -
CS53L32A-BZ Analog Input Characteristics for VA = 3.0 V
Dynamic Range
A-weighted
unweighted
89 96
86 93
-
-
High-rate Mode
Min Typ Max Unit
- 77 - dB
- 76 - dB
- 90 - dB
- 0.1 - dB
- - 0 LSB
-5% VA/3.6 +5% Vrms
- 100 - ppm/°C
10 -
- kΩ
- - 15 pF
87 94 - dB
84 91 - dB
- -88 -81 dB
- -71 - dB
- -31 - dB
- -86 - dB
- -68 - dB
- -28 - dB
- 89 - dB
- 86 - dB
- 86 - dB
- 83 - dB
- 84 - dB
- 82 - dB
91 98 - dB
88 95 - dB
DS513F1
5
5 Page 
CS53L32A
SCLK
LRCK
t sclkl
t sclkh
t slrd
SDOUT
t dss
MSB
Figure 1. SCLK to LRCK and SDOUT, Slave Mode
t sclkw
SCLK
LRCK
SDOUT
t slrd
t sdo
MSB
MSB-1
Figure 2. SCLK to LRCK and SDOUT, Master Mode
LRCK Input
6 ns
10 ns
MCLK Input
No rising edge of MCLK allowed within this
timing window.
Figure 3. Relationship Required Between LRCK and MCLK in Slave Mode
DS513F1
11
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet CDB53L32A.PDF ] | |
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