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PDF CDB391A Data sheet ( Hoja de datos )

Número de pieza CDB391A
Descripción STEREO DAC
Fabricantes Cirrus Logic 
Logotipo Cirrus Logic Logotipo



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CS4391A
24-Bit, 192 kHz Stereo DAC with Volume Control
Features
Complete Stereo DAC System: Interpolation,
D/A, Output Analog Filtering
108 dB Dynamic Range
94 dB THD+N
Direct Stream Digital Mode
Low Clock Jitter Sensitivity
+5 V Power Supply
ATAPI Mixing
On-Chip Digital De-emphasis for 32, 44.1,
and 48 kHz
Volume Control with Soft Ramp
– 119 dB Attenuation
– 1 dB Step Size
– Zero Crossing Click-Free Transitions
Direct Interface with 5 V to 1.8 V Logic
I
Description
The CS4391A is a complete stereo digital-to-analog sys-
tem including digital interpolation, fourth-order delta-
sigma digital-to-analog conversion, digital de-emphasis,
volume control, channel mixing and analog filtering. The
advantages of this architecture include: ideal differential
linearity, no distortion mechanisms due to resistor
matching errors, no linearity drift over time and tempera-
ture and a high tolerance to clock jitter.
The CS4391A accepts PCM data at sample rates from
4 kHz to 192 kHz, DSD audio data, consumes very little
power and operates over a wide power supply range.
These features are ideal for DVD, A/V receivers, CD and
set-top box systems.
ORDERING INFORMATION
CS4391A-KS 20-pin SOIC
-10 to 70 °C
CS4391A-KZ 20-pin TSSOP
-10 to 70 °C
CS4391A-KZZ 20-pin TSSOP, Lead Free -10 to 70 °C
CDB4391A Evaluation Board
M1 M2 M0
(SDA/CDIN) M3 (SCL/CCLK) (AD0/CS) AMUTEC BMUTEC
CMOUT FILT+
RST
SCLK
LRCK
SDATA
MODE SELECT
(CONTROL PORT)
EXTERNAL
MUTE CONTROL
REFERENCE
SERIAL
PORT
INTERPOLATION
FILTER
INTERPOLATOR
FILTER
VOLUME
CONTROL
MIXER
VOLUME
CONTROL
∆Σ
DAC
∆Σ
DAC
ANALOG
FILTER
ANALOG
FILTER
AOUTA+
AOUTA-
AOUTB+
AOUTB-
MCLK
Preliminary Product Information
www.cirrus.com
This document contains information for a new product.
Cirrus Logic reserves the right to modify this product without notice.
©Copyright Cirrus Logic, Inc. 2004
(All Rights Reserved)
JUL ‘04
DS600PP3
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CDB391A pdf
CS4391A
1. CHARACTERISTICS/SPECIFICATIONS
(Min/Max performance characteristics and specifications are guaranteed over the Specified Operating Conditions.
Typical performance characteristics are derived from measurements taken at TA = 25 °C, VA = 5.0 V)
SPECIFIED OPERATING CONDITIONS (AGND = 0V; all voltages with respect to ground.)
Parameters
Symbol Min Typ Max Units
DC Power Supply
VA 4.75 5.0 5.25
VL 1.8 - VA
V
V
Specified Temperature Range
-KS & -KZ TA
-10
-
70 °C
ABSOLUTE MAXIMUM RATINGS (AGND = 0 V; all voltages with respect to ground.)
DC Power Supply
Parameters
Symbol
VA
VL
Min
-0.3
-0.3
Max Units
6.0 V
VA V
Input Current, Any Pin Except Supplies
Digital Input Voltage
Ambient Operating Temperature (power applied)
Storage Temperature
Iin
VIND
TA
Tstg
- ±10 mA
-0.3 VL+0.4
V
-55 125 °C
-65 150 °C
WARNING: Operation at or beyond these limits may result in permanent damage to the device. Normal operation is
not guaranteed at these extremes.
DS600PP3
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CDB391A arduino
CS4391A
SWITCHING CHARACTERISTICS - I2C CONTROL PORT (Inputs: logic 0 = AGND,
logic 1 = VL)
I2C® Mode
SCL Clock Frequency
Parameter
RST Rising Edge to Start
Bus Free Time Between Transmissions
Start Condition Hold Time (prior to first clock pulse)
Clock Low time
Clock High Time
Setup Time for Repeated Start Condition
SDA Hold Time from SCL Falling
(Note 7)
SDA Setup time to SCL Rising
Rise Time of Both SDA and SCL Lines
Fall Time of Both SDA and SCL Lines
Setup Time for Stop Condition
Symbol
fscl
tirs
tbuf
thdst
tlow
thigh
tsust
thdd
tsud
tr
tf
tsusp
Min
-
500
4.7
4.0
4.7
4.0
4.7
0
250
-
-
4.7
Max
100
-
-
-
-
-
-
-
-
1
300
-
Unit
KHz
ns
µs
µs
µs
µs
µs
µs
ns
µs
ns
µs
Notes: 7. Data must be held for sufficient time to bridge the 300 ns transition time of SCL.
RST
t irs
Stop Start
R e p e a te d
S ta rt
SDA
t buf t hdst
t high
t hdst
tf
SCL
tt
lo w hdd
t sud t sust
tr
Figure 3. I2C Control Port Timing
Stop
t susp
DS600PP3
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