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PDF KM62U256C Data sheet ( Hoja de datos )
| Número de pieza | KM62U256C | |
| Descripción | Low Power AND Low Vcc CMOS Static RAM | |
| Fabricantes | Samsung semiconductor | |
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KM62V256C, KM62U256C Family
CMOS SRAM
32Kx8 bit Low Power & Low Vcc CMOS Static RAM
FEATURE SUMMARY
GENERAL DESCRIPTION
• Process Technology : 0.7µm CMOS
• Organization : 32K x 8
• Power Supply Voltage
KM62V256C family : 3.3V ± 0.3V
KM62U256C family : 3.0V ± 0.3V
• Low Data Retention Voltage : 2V(Min)
• Three state output and TTL Compatible
• Package Type : JEDEC Standard
28-SOP, 28-TSOP(I)-Forward/Reverse
The KM62V256C and KM62U256C family are fabricated
by SAMSUNG's advanced CMOS process technology. The
family can support various operating temperature ranges
and has various package types for user flexibility of system
design. The family also support low data retention voltage
for battery back-up operation with low data retention
current.
PRODUCT FAMILY
Product
List
Operating Vcc Range
Temp.
Speed
(ns)
KM62V256CL-L Commercial
KM62U256CL-L (0~70 °C)
KM62V256CLE-L Extended
KM62U256CLE-L (-25~85 °C)
KM62V256CLI-L Industrial
KM62U256CLI-L (-40~85 °C)
3.0~3.6V
2.7~3.3V
3.0~3.6V
2.7~3.3V
3.0~3.6V
2.7~3.3V
70*/100
85*/100
70*/100
85*/100
70*/100
85*/100
* measured with 30pF test load
** the device with 100ns SOP package in 3.0~3.6V Vcc range is not produced.
PKG Type
28-SOP**
28-TSOP(I) R/F
28-SOP**
28-TSOP(I) R/F
28-SOP**
28-TSOP(I) R/F
Power Dissipation
Standby
(Isb1, Max)
10 µA
Operating
(Icc2)
10 µA
20 µA
15 µA
35mA
20 µA
15 µA
PIN DESCRIPTION
FUNCTIONAL BLOCK DIAGRAM
A14 1
28 Vcc /OE 1
28 A10
A12 2
A11 2
27 /WE A9 3
27 /CS
26 IO8
A7 3
26 A13 A8 4
25 IO7
A13 5
24 IO6
A6 4
25 A8 /WE 6
28-Pin TSOP 23 IO5
A5 5
24 A9 Vcc 7
22 IO4
A4 6
Type I - ForwardA14 8
23 A11 A12 9
21 Vss
20 IO3
A3 7 28-Pin SOP 22 /OE A7 10
19 IO2
A6 11
18 IO1
A2 8
21 A10 A5 12
17 A0
A1 9
20 /CS A4 13
16 A1
A0 10
A3 14
19 I/O8
15 A2
I/O1
11
18 I/O7
I/O2
I/O3
Vss
12
13
14
17
I/O6
A3
14
28 A2
16 I/O5 A4 13
27 A1
15
I/O4 A5
A6
12
11
26 A0
25 IO1
A7 10
A12 9
28-Pin TSOP
24 IO2
23 IO3
A14 8
Vcc 7
Type I - Reverse
22
21
Vss
IO4
/WE 6
20 IO5
A13 5
19 IO6
A8 4
18 IO7
A9 3
17 IO8
A11 2
16 /CS
/OE 1
15 A10
A0~2, A9~11
A3~A8
A12~14
Y-Decoder
Cell Array
I/O1~8
I/O Buffer
/CS, /WE
/OE
Pin Name
A0~A14
/WE
/CS
/OE
I/O1~I/O8
Vcc
Vss
Function
Address Inputs
Write Enable Input
Chip Select Input
Output Enable Input
Data Input/Output
Power
Ground
ELECTRONICS
-1-
Revision 04
April 1996
1 page  
KM62V256C, KM62U256C Family
CMOS SRAM
TEST CONDITIONS (2. Temperature and Vcc Conditions)
Product Family
KM62V256CL-L
KM62V256CLE-L
KM62V256CLI-L
KM62U256CL-L
KM62U256CLE-L
KM62U256CLI-L
Temperature
0~70 °C
-25~85 °C
-40~85 °C
0~70 °C
-25~85 °C
-40~85 °C
* all the AC parameters are measured with 30pF test load
Power Supply(Vcc)
3.3V +/- 0.3
3.3V +/- 0.3
3.3V +/- 0.3
3.0V +/- 0.3
3.0V +/- 0.3
3.0V +/- 0.3
Speed Bin
70*/100ns
70*/100ns
70*/100ns
85*/100ns
85*/100ns
85*/100ns
Comments
Commercial
Extended
Industrial
Commercial
Extended
Industrial
PARAMETER LIST FOR EACH SPEED BIN
Parameter List
Symbol
Read Read cycle time
tRC
Address access time
tAA
Chip select to output
tCO
Output enable to valid output
tOE
Chip select to low-Z output
tLZ
Output enable to low-Z output tOLZ
Chip disable to high-Z output
tHZ
Output disable to high-Z output tOHZ
Output hold from address change tOH
Write Write cycle time
tWC
Chip select to end of write
tCW
Address set-up time
tAS
Address valid to end of write
tAW
Write pulse width
tWP
Write recovery time
tWR
Write to output high-Z
tWHZ
Data to write time overlap
tDW
Data hold from write time
tDH
End write to output low-Z
tOW
Speed Bins
70ns
85ns
Min Max Min Max
70 - 85 -
- 70 - 85
- 70 - 85
- 35 - 40
10 - 10 -
5 -5-
0 30 0 35
0 30 0 35
5 - 10 -
70 - 85 -
60 - 70 -
0 -0-
60 - 70 -
50 - 60 -
0 -0-
0 25 0 25
50 - 60 -
0 -0-
5 - 10 -
100ns
Min Max
100 -
- 100
- 100
- 50
10 -
5-
0 35
0 35
15 -
100 -
70 -
0-
70 -
60 -
0-
0 30
60 -
0-
10 -
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ELECTRONICS
-5-
Revision 04
April 1996
5 Page 
KM62V256C, KM62U256C Family
CMOS SRAM
TECHNICAL INFORMATION
1) Icc2 characteristics by temperature variation
All the values in this graph are depicted by the relative value with the maximum value
measured at 3.3V Vcc and -40° Ctemperature. The basic relative value of Icc2 at that
condition is set into 1.
Icc2 v.s Temperature
1.000
0.900
0.800
0.700
0.600
0.500
-40
-10
0 25 40 70 85
Temerature( ¡ É)
3.0V
Device
3.3V
Device
2) Isb1(CMOS Level Standby Current) characteristics by temperature variation
All the values in this graph are depicted by the relative value with the maximum value
measured at 3.0V Vcc and 85° Ctemperature. The basic relative value of Isb1 at that
condition is set into 1.
Isb1 v.s Temperature
1.00
0.80
0.60
0.40
0.20
0.00
-40
-10
0 25 40
Temperature( ¡ É)
70
85
2.7V
3.0V
ELECTRONICS
- 11 -
Revision 04
April 1996
11 Page | ||
| Páginas | Total 12 Páginas | |
| PDF Descargar | [ Datasheet KM62U256C.PDF ] | |
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