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PDF KM62U256D Data sheet ( Hoja de datos )
| Número de pieza | KM62U256D | |
| Descripción | Low Power and Low Voltage CMOS Static RAM | |
| Fabricantes | Samsung semiconductor | |
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KM62V256D, KM62U256D Family
Document Title
32Kx8 bit Low Power and Low Voltage CMOS Static RAM
CMOS SRAM
Revision History
Revision No.
0.0
History
Initial draft
1.0 Finalize
- Add 70ns part in KM62U256D Family
- Show ICC read only, and increased value
ICC = 2mA →ICC Read = 5mA
- Seperate ICC1 read and write
ICC1 = 5mA→ICC1 Read = 5mA, ICC1 Write = 10mA
- Improved standby current(ISB1)
Commercial part : 10µA→5µA
Extended and Industrial part : 20µA→5µA
- Improved VIL(Min.) : 0.4V→0.6V
- Improved power dissipation : 0.7W→1W
Draft Data
April 1, 1997
November 12, 1997
Remark
Preliminary
Final
The attached datasheets are provided by SAMSUNG Electronics. SAMSUNG Electronics CO, LTD. reserve the right to change the specifications and
products. SAMSUNG Electronics will answer to your questions about device. If you have any questions, please contact the SAMSUNG branch offices.
1 Revision 1.0
November 1997
1 page  
KM62V256D, KM62U256D Family
AC OPERATING CONDITIONS
TEST CONDITIONS (Test Load and Test Input/Output Reference)
Input pulse level : 0.4 to 2.4V
Input rising and falling time : 5ns
Input and output reference voltage : 1.5V
Output load (See right) :CL=100pF+1TTL
CL1)=30pF+1TTL
1. Refer to AC CHARACTERISTICS
CMOS SRAM
CL1)
1. Including scope and jig capacitance
AC CHARACTERISTICS (KM62V256D Family:Vcc=3.0~3.6V, KM62U256D Family:Vcc=2.7~3.3V
Commercial product :TA=0 to 70°C, Extended product :TA=-25 to 85°C, Industrial product :TA=-40 to 85°C)
Parameter List
Read cycle time
Address access time
Chip select to output
Read
Output enable to valid output
Chip select to low-Z output
Output enable to low-Z output
Chip disable to high-Z output
Output disable to high-Z output
Output hold from address
Write cycle time
Chip select to end of write
Address set-up time
Address valid to end of write
Write
Write pulse width
Write recovery time
Write to output high-Z
Data to write time overlap
Data hold from write time
End write to output low-Z
1. The parameter is measured with 30pF test load
Symbol
tRC
tAA
tCO
tOE
tLZ
tOLZ
tHZ
tOHZ
tOH
tWC
tCW
tAS
tAW
tWP
tWR
tWHZ
tDW
tDH
tOW
701)ns
Min Max
70 -
- 70
- 70
- 35
10 -
5-
0 30
0 30
5-
70 -
60 -
0-
60 -
50 -
0-
0 25
30 -
0-
5-
Speed Bins
85ns
Min Max
85 -
- 85
- 85
- 40
10 -
5-
0 30
0 30
10 -
85 -
70 -
0-
70 -
60 -
0-
0 25
35 -
0-
10 -
100ns
Min Max
100 -
- 100
- 100
- 50
10 -
5-
0 35
0 35
15 -
100 -
80 -
0-
80 -
70 -
0-
0 35
40 -
0-
10 -
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
DATA RETENTION CHARACTERISTICS
Item
Vcc for data retention
Data retention current
Data retention set-up time
Recovery time
Symbol
VDR
IDR
tSDR
tRDR
Test Condition
CS≥Vcc-0.2V
Vcc=3.0V, CS≥Vcc-0.2V
See data retention waveform
Min Typ Max Unit
2.0 - 3.6 V
- 5 µA
0 - - ms
5- -
5 Revision 1.0
November 1997
5 Page | ||
| Páginas | Total 9 Páginas | |
| PDF Descargar | [ Datasheet KM62U256D.PDF ] | |
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