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PDF ADS8504 Data sheet ( Hoja de datos )
| Número de pieza | ADS8504 | |
| Descripción | SAMPLING CMOS ANALOG-TO-DIGITAL CONVERTER | |
| Fabricantes | Burr-Brown | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de ADS8504 (archivo pdf) en la parte inferior de esta página. Total 19 Páginas | ||
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BurrĆBrown Products
from Texas Instruments
ADS8504
SLAS434 – JUNE 2005
12-BIT 250-KSPS SAMPLING CMOS ANALOG-TO-DIGITAL CONVERTER
FEATURES
• 250-kHz Sampling Rate
• Standard ±10-V Input Range
• 73-dB SINAD With 45-kHz Input
• ±0.45 LSB Max INL
• ±0.45 LSB Max DNL
• 12 Bit No Missing Code
• ±1 LSB Bipolar Zero Errors
• ±0.4 PPM/°C Bipolar Zero Error Drift
• Single 5-V Supply Operation
• Pin-Compatible With ADS7804/05 (Low Speed)
and 16-Bit ADS8505
• Uses Internal or External Reference
• Full Parallel Data Output
• 70-mW Typ Power Dissipation at 250 KSPS
• 28-Pin SOIC Package
APPLICATIONS
• Industrial Process Control
• Data Acquisition Systems
• Digital Signal Processing
• Medical Equipment
• Instrumentation
DESCRIPTION
The ADS8504 is a complete 12-bit sampling A/D
converter using state-of-the-art CMOS structures. It
contains a complete 12-bit, capacitor-based, SAR
A/D with S/H, reference, clock, interface for
microprocessor use, and 3-state output drivers.
The ADS8504 is specified at a 250-kHz sampling rate
over the full temperature range. Precision resistors
provide an industry standard ±10-V input range, while
the innovative design allows operation from a single
+5-V supply, with power dissipation under 100 mW.
The ADS8504 is available in a 28-pin SOIC package
and is fully specified for operation over the industrial
-40°C to 85°C temperature range.
Clock
Successive Approximation Register and Control Logic
R/C
CS
BYTE
BUSY
9.8 kΩ
± 10 V Input
5 kΩ
CAP
2 kΩ
REF
CDAC
Buffer
4 kΩ
Internal
+2.5 V Ref
Comparator
Output
Latches
and
Three
State
Drivers
Three
State
Parallel
Data
Bus
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2005, Texas Instruments Incorporated
1 page  
ADS8504
www.ti.com
SLAS434 – JUNE 2005
DEVICE INFORMATION (continued)
Terminal Functions
TERMINAL
NAME
DW NO.
AGND1
2
AGND2
5
BUSY
26
BYTE
CAP
CS
DGND
D11 (MSB)
23
4
25
14
6
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0 (LSB)
7
8
9
10
11
12
13
15
16
17
18
DZ 19
DZ 20
DZ 21
DZ 22
R/C 24
REF
VANA
VDIG
VIN
3
27
28
1
DIGITAL
I/O
DESCRIPTION
Analog ground. Used internally as ground reference point.
Analog ground.
O At the start of a conversion, BUSY goes low and stays low until the conversion is
completed and the digital outputs have been updated.
I Selects 8 most significant bits (low) or 8 least significant bits (high).
Reference buffer capacitor. 2.2-µF tantalum capacitor to ground.
I Internally ORed with R/C. If R/C low, a falling edge on CS initiates a new conversion.
Digital ground.
O Data bit 11. Most significant bit (MSB) of conversion results. Hi-Z state when CS is
high, or when R/C is low.
O Data bit 10. Hi-Z state when CS is high, or when R/C is low.
O Data bit 9. Hi-Z state when CS is high, or when R/C is low.
O Data bit 8. Hi-Z state when CS is high, or when R/C is low.
O Data bit 7. Hi-Z state when CS is high, or when R/C is low.
O Data bit 6. Hi-Z state when CS is high, or when R/C is low.
O Data bit 5. Hi-Z state when CS is high, or when R/C is low.
O Data bit 4. Hi-Z state when CS is high, or when R/C is low.
O Data bit 3. Hi-Z state when CS is high, or when R/C is low.
O Data bit 2. Hi-Z state when CS is high, or when R/C is low.
O Data bit 1. Hi-Z state when CS is high, or when R/C is low.
O Data bit 0. Least significant bit (LSB) of conversion results. Hi-Z state when CS is high,
or when R/C is low.
O Low when CS low, R/C high. Hi-Z state when CS is high, or when R/C is low.
O Low when CS low, R/C high. Hi-Z state when CS is high, or when R/C is low.
O Low when CS low, R/C high. Hi-Z state when CS is high, or when R/C is low.
O Low when CS low, R/C high. Hi-Z state when CS is high, or when R/C is low.
I With CS low and BUSY high, a falling edge on R/C initiates a new conversion. With CS
low, a rising edge on R/C enables the parallel output.
Reference input/output. 2.2-µF tantalum capacitor to ground.
Analog supply input. Nominally +5 V. Decouple to ground with 0.1-µF ceramic and
10-µF tantalum capacitors.
Digital supply input. Nominally +5 V. Connect directly to pin 27. Must be ≤ VANA.
Analog input.
5
5 Page 
www.ti.com
ADS8504
SLAS434 – JUNE 2005
Bit 11 (MSB) 6
Bit 10 7
Bit 9 8
Bit 8 9
Bit 7 10
Bit 6 11
Bit 5 12
Bit 4 13
14
BYTE LOW
23
ADS8504
22 Low
21 Low
20 Low
19 Low
18 Bit 0 (LSB)
17 Bit 1
16 Bit 2
15 Bit 3
Bit 3 6
Bit 2 7
Bit 1 8
Bit 0 9
Low 10
Low 11
Low 12
Low 13
14
BYTE HIGH
23
+5 V
ADS8504
22 Bit 4
21 Bit 5
20 Bit 6
19 Bit 7
18 Bit 8
17 Bit 9
16 Bit 10
15 Bit 11 (MSB)
Figure 18. Bit Locations Relative to State of BYTE (Pin 23)
R/C
BUSY
MODE
tpd
td2
Acquire
tw1
tc
ta1
tw2
Convert
td1
Acquire
Convert
tconv
tacq
DATA BUS
Previous
Data Valid
tdis
Hi−Z
Previous
Data Valid
tv
Not Valid
td3
Data Valid
Hi−Z
Data Valid
Figure 19. Conversion Timing with Outputs Enabled after Conversion (CS Tied Low)
tsu
R/C
tsu tsu
tsu
CS
BUSY
tw1
tpd
tw2
td2
MODE Acquire
Convert
tconv
Acquire
DATA BUS
Hi−Z State
Data Valid Hi−Z State
ten tdis
Figure 20. Using CS to Control Conversion and Read Timing
11
11 Page | ||
| Páginas | Total 19 Páginas | |
| PDF Descargar | [ Datasheet ADS8504.PDF ] | |
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