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PDF AD9929 Data sheet ( Hoja de datos )
| Número de pieza | AD9929 | |
| Descripción | CCD Signal Processor | |
| Fabricantes | Analog Devices | |
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FEATURES
36 MSPS correlated double sampler (CDS)
12-bit 36 MHz A/D converter
On-chip vertical driver for CCD image sensor
On-chip horizontal driver for CCD image sensor
6 dB to 40 dB variable gain amplifier (VGA)
Black level clamp with variable level control
Complete on-chip timing generator
Precision Timing core with 0.58 ns resolution
2-phase H-clock modes
4-phase vertical transfer clocks
Electronic and mechanical shutter modes
On-chip sync generator with external sync option
64-lead, plastic ball, 9 × 9 grid array Pb-free package
APPLICATION
Digital still cameras
Digital video camcorders
CCD Signal Processor with
Precision Timing™ Generator
AD9929
PRODUCT DESCRIPTION
The AD9929 is a highly integrated CCD signal processor for
digital still camera and digital video camera applications. It
includes a complete analog front end with A/D conversion,
combined with a full-function, programmable timing generator.
The AD9929 also includes horizontal and vertical clock drivers,
which allow direct connection to the CCD image sensor.
The AD9929 is specified at pixel rates of up to 36 MHz. The
analog front end includes black level clamping, a CDS, a VGA,
and a 12-bit A/D converter. The timing generator provides all
the necessary CCD clocks: RG-clock, H-clocks, V-clocks, sensor
gate pulses, a substrate clock, and a substrate bias pulse. Oper-
ation is programmed using a 3-wire serial interface.
The AD9929 is packaged in a 64-lead CSPBGA. It is specified
over an operating temperature range of −25°C to +85°C.
FUNCTIONAL BLOCK DIAGRAM
REFT REFB
CCDIN
AD9929
CDS
6dB TO 40dB
VGA
VREF
ADC
12
DOUT
VSUB
RG
H1, H2
V1, V2,
V3, V4
SUBCK
HORIZONTAL
DRIVERS
2
4
VERTICAL
DRIVERS
INTERNAL CLOCKS
PRECISION
TIMING
GENERATOR
SYNC
GENERATOR
CLAMP
INTERNAL
REGISTERS
DCLK1
FD/DCLK2
MSHUT
STROBE
HD VD SYNC CLI
Figure 1.
SL SCKS DI
Rev. A
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.326.8703 © 2004 Analog Devices, Inc. All rights reserved.
1 page  
AD9929
TIMING SPECIFICATIONS
Table 4. CL = 20 pF, AVDD = DVDD = DRVDD = 3.0 V, fCLI = 36 MHz, unless otherwise noted.
Parameter
Symbol
Min Typ Max Unit
MASTER CLOCK, CLI
CLI Clock Period
tCONV
27.8
ns
CLI High/Low Pulse Width
13.9 ns
Delay from CLI Rising Edge to Internal Pixel Position 0
tCLIDLY
6 ns
AFE CLAMP PULSES1
CLPOB Pulse Width
4 10
Pixels
AFE SAMPLE LOCATION1 (See Figure 17)
SHP Sample Edge to SHD Sample Edge
TS1 20 25
Pixels
DATA OUTPUTS
Output Delay from DCLK1 Rising Edge (See Figure 19)
tOD 9 ns
Pipeline Delay from SHP/SHD Sampling (See Figure 70)
9 Cycles
SERIAL INTERFACE (See Figure 10 and Figure 11)
tDV
Maximum SCK Frequency
fSCLK
10
MHz
SL to SCK Setup Time
tLS 10
ns
SCK to SL Hold Time
tLH 10
ns
SDATA Valid to SCK Rising Edge Setup
tDS 10
ns
SCK Falling Edge to SDATA Valid Hold
tDH 10
ns
SCK Falling Edge to SDATA Valid Read
tOD 10
ns
1 Parameter is programmable.
VERTICAL DRIVER SPECIFICATIONS
Table 5. V1 to V4 load = no load, SUBCK load = no load, VDD = 3.0 V, VL = −7.5 V, VH1 = VH2 = +15.0 V, VM1 = VM2 = GND,
fCLI = 36 MHz, unless otherwise noted.
Parameter
Symbol
Min
Typ
Max Unit
LOGIC INPUTS
High Level Input Voltage
VIH 0.8 (VDD)
VDD V
Low Level Input Voltage
VIL 0
0.3 (VDD)
V
Propagation Delays, Rise/Fall Times and Output Currents
V1 and V3 Outputs (See Figure 43)
Delay Times
VL to VM1
tPLM1
100 ns
VM1 to VH1
tPMH 100 ns
VH1 to VM1
tPHM 50 ns
VM1 to VL
tPML1
50 ns
Rise Times
VL to VM1
tR1 500 ns
VM1 to VH1
tR2 500 ns
Fall Times
VH1 to VM1
tF1 500 ns
VM1 to VL
tF2 500 ns
Output Currents
V1 or V3 @ VL = −7.25 V
10.0 mA
V1 or V3 @ VM1 = −0.25 V
−5.0 mA
V1 or V3 @ VM1 = +0.25 V
5.0 mA
V1 or V3 @ VH1 = +14.75 V
−7.2 mA
Rev. A | Page 5 of 64
5 Page 
AD9929
Table 8. Control Register Address Map
Bit Default
Address Content Width Value
0x00
(23:0) 24
000000
0x01
23
1
0
(22:21) 2
(20:18)
17
16
(15:14)
13
(12:10)
(9:8)
3
1
1
2
1
3
2
0
1
0
0
0
0
0
0x02
0x03
0x04
0x05
7
6
5
4
(3:1)
0
(23:22)
(21:16)
(15:14)
(13:8)
(7:6)
(5:0)
(23:17)
16
(15:14)
(13:8)
(7:6)
(5:0)
(23:16)
15
(14:12)
11
(10:8)
(7:3)
(2:0)
(23:10)
9
8
(7:2)
1
1
1
1
1
3
1
2
6
2
6
2
6
7
1
2
6
2
6
8
1
3
1
3
5
3
14
1
1
6
1
0
0
1
1
0
0
0
0x34
0
0x18
0
0x0B
0x00
0
0
0x00
0
0x10
0x80
–
5
0
5
0x00
2
0x0000
0
0
00
0
0 11
Register Name
SW_RESET
Unused
XSUBCKSUPPRESS
Unused
HBLKMASK
SYNCPOL
Unused
XSUBCKMODE_HP
Unused
MSHUTPAT
MSHUT/VGATE_EN
Unused
CLPOB_CONT
CLPOB_MODE
Unused
VDMODE
Unused
SHDLOC
Unused
SHPLOC
DCLKPHASE
DOUTPHASE
Unused
H1BLKRETIME
Unused
H1POSLOC
Unused
RGNEGLOC
REFBLACK
Unused
H2DRV
Unused
H1DRV
Unused
RGDRV
Unused
AFESTBY
DIGSTBY
Unused
OUTCONT_REG
OUTCONT_ENB
Register Description
Software Reset = 000000 (Reset All Registers to Default )
Suppress XSUBCK (00 = No Suppression, 01 = Suppress First XSUBCK
After Last VSG Line Pulse, 10 = Suppress All XSUBCKs, Except Final
XSUBCK, 11 = No Suppression)
Test Mode. Should Be Set = 0
Masking Polarity for H1 During Blanking Period (0 = Low, 1 = High)
External SYNC Active Polarity (0 = Active Low)
High Precision Shutter Mode Operation
(0 = Single Pulse, 1 = Multiple Pulse)
Selects MSHUT Pattern. (See Figure 51)
(0 = Mshutpat0,1 = Mshutpat1,2 = Mshutpat2, 3 = Mshutpat3)
MSHUT Masking of VGATE Input (0 = MSHUT Does Not Mask VGATE,
1 = MSHUT Does Mask VGATE)
CLPOB Control (0 = CLPOB Off, 1 = CLPOB On)
CLPOB CCD Region Control (See Table 19)
VD Synchronous/Asynchronous Mode Setting
(0 = VD Synchronous, 1 = VD Asynchronous )
SHD Sample Location
SHP Sample Location
DCLK Pulse Adjustment
Data Output [11:0] Phase Adjustment
Retimes the H1 HBLK to Internal Clock
H1 Positive Edge Location
RG Negative Edge Location
Black Level Clamp
H2 Drive Strength (0 = Off, 1 = 4.3 mA, 2 = 8.6 mA, 3 = 12.9 mA,
4 = 17.2 mA, 5 = 21.5 mA, 6 = 25.8 mA, 7 = 30.1 mA)
H1 Drive Strength (0 = Off, 1 = 4.3 mA, 2 = 8.6 mA, 3 = 12.9 mA,
4 = 17.2 mA, 5 = 21.5 mA, 6 = 25.8 mA, 7 = 30.1 mA)
RG Drive Strength (0 = Off, 1 = 2.15 mA, 2 = 4.2 mA, 3 = 6.45 mA,
4 = 8.6 mA, 5 = 10.75 mA, 6 = 12.9 mA, 7 = 15.05 mA)
AFE Standby (0 = Standby, 1 = Normal Operation)
Digital Standby (0 = Standby, 1 = Normal Operation)
Internal OUTCONT Signal Control
(0 = Digital Outputs Held at Fixed DC Level, 1 = Normal Operation)
External OUTCONT Signal Input Pin 43 Control (0 = Pin Enabled,
1 = Pin Disabled)
Rev. A | Page 11 of 64
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet AD9929.PDF ] | |
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