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PDF 74LVC1G57 Data sheet ( Hoja de datos )
| Número de pieza | 74LVC1G57 | |
| Descripción | Low-power configurable multiple function gate | |
| Fabricantes | NXP Semiconductors | |
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74LVC1G57
Low-power configurable multiple function gate
Rev. 01 — 6 September 2004
Product data sheet
1. General description
The 74LVC1G57 is a high-performance, low-power, low-voltage, Si-gate CMOS device,
superior to most advanced CMOS compatible TTL families.
Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of this
device in a mixed 3.3 V and 5 V environment.
This device is fully specified for partial power-down applications using Ioff. The Ioff circuitry
disables the output, preventing the damaging backflow current through the device when it
is powered down.
The 74LVC1G57 provides configurable multiple functions. The output state is determined
by eight patterns of 3-bit input. The user can choose the logic functions AND, OR, NAND,
NOR, XNOR, inverter and buffer. All inputs can be connected to VCC or GND.
All inputs (A, B and C) have Schmitt-trigger action. They are capable of transforming
slowly changing input signals into sharply defined, jitter-free output signals.
2. Features
s Wide supply voltage range from 1.65 V to 5.5 V
s 5 V tolerant input/output for interfacing with 5 V logic
s High noise immunity
s Complies with JEDEC standard:
x JESD8-7 (1.65 V to 1.95 V)
x JESD8-5 (2.3 V to 2.7 V)
x JESD8B/JESD36 (2.7 V to 3.6 V).
s ±24 mA output drive (VCC = 3.0 V)
s ESD protection:
x HBM EIA/JESD22-A114-B exceeds 2000 V
x MM EIA/JESD22-A115-A exceeds 200 V.
s CMOS low power consumption
s Latch-up performance exceeds 250 mA
s Direct interface with TTL levels
s Inputs accept voltages up to 5 V
s Multiple package options
s Specified from −40 °C to +85 °C and −40 °C to +125 °C.
1 page  
Philips Semiconductors
74LVC1G57
Low-power configurable multiple function gate
VCC
A
C
Y
1 6C
25
A
C
Y
A3
4Y
001aab586
Fig 6. 2-input NAND gate with input C
inverted or 2-input OR gate with
inverted A input.
VCC
A
C
Y
1 6C
25
A
C
Y
A3
4Y
001aab587
Fig 7. 2-input NOR gate or 2-input AND
gate with both inputs inverted.
VCC
B 1 6C
B
C
Y
25
3 4Y
001aab588
Fig 8. 2-input XNOR gate.
AY
Fig 9. Inverter.
VCC
1
2
A3
6
5
4Y
001aab589
VCC
Fig 10. Buffer.
B1
6
BY
25
3 4Y
001aab590
9. Limiting values
9397 750 13722
Product data sheet
Table 7: Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to
GND (ground = 0 V).
Symbol Parameter
Conditions
Min Max
Unit
VCC supply voltage
−0.5 +6.5
V
IIK input diode current VI < 0 V
- −50
mA
VI input voltage
[1] −0.5 +6.5
V
IOK
output diode current
VO > VCC or VO < 0 V
- ±50
mA
VO output voltage
active mode
[1] [2] −0.5 +6.5
V
Power-down mode
[1] [2] −0.5 +6.5
V
IO
output source or sink
VO = 0 V to VCC
current
- ±50
mA
Rev. 01 — 6 September 2004
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
5 of 18
5 Page 
Philips Semiconductors
74LVC1G57
Low-power configurable multiple function gate
Table 13: Transfer characteristics …continued
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter
Conditions
VH hysteresis voltage (VT+ − VT−) see Figure 13, 14, 15 and 16
VCC = 1.8 V
VCC = 2.3 V
VCC = 3.0 V
VCC = 4.5 V
Tamb = −40 °C to +125 °C
VCC = 5.5 V
VT+ positive-going threshold see Figure 13, 14, 15 and 16
voltage
VCC = 1.8 V
VCC = 2.3 V
VCC = 3.0 V
VCC = 4.5 V
VCC = 5.5 V
VT−
negative-going threshold
see Figure 13, 14, 15 and 16
voltage
VCC = 1.8 V
VCC = 2.3 V
VCC = 3.0 V
VCC = 4.5 V
VCC = 5.5 V
VH hysteresis voltage (VT+ − VT−) see Figure 13, 14, 15 and 16
VCC = 1.8 V
VCC = 2.3 V
VCC = 3.0 V
VCC = 4.5 V
VCC = 5.5 V
Min
0.30
0.40
0.50
0.71
0.71
0.67
1.08
1.47
2.13
2.58
0.30
0.58
0.80
1.21
1.45
0.23
0.34
0.44
0.65
0.65
[1] Typical values are measured at Tamb = 25 °C.
Typ
0.48
0.64
0.75
0.97
1.13
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Max
0.62
0.80
1.00
1.20
1.40
1.20
1.60
2.00
2.74
3.33
0.75
1.03
1.33
1.93
2.32
0.62
0.80
1.00
1.20
1.40
Unit
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
15. Waveforms transfer characteristics
VT+
VO VI VH
VT−
9397 750 13722
Product data sheet
VH
VT− VT+
VI
mna207
Fig 13. Transfer characteristic.
VO
mna208
VT+ and VT− limits are at 70 % and
20 %.
Fig 14. Definition of VT+, VT− and VH.
Rev. 01 — 6 September 2004
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
11 of 18
11 Page | ||
| Páginas | Total 18 Páginas | |
| PDF Descargar | [ Datasheet 74LVC1G57.PDF ] | |
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