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PDF SC16IS752 Data sheet ( Hoja de datos )

Número de pieza SC16IS752
Descripción (SC16IS752 / SC16IS762) Dual UART
Fabricantes NXP Semiconductors 
Logotipo NXP Semiconductors Logotipo



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SC16IS752/SC16IS762
Dual UART with I2C-bus/SPI interface, 64 bytes of transmit
and receive FIFOs, IrDA SIR built-in support
Rev. 06 — 19 December 2006
Product data sheet
1. General description
The SC16IS752/SC16IS762 is an I2C-bus/SPI bus interface to a dual-channel high
performance UART offering data rates up to 5 Mbit/s, low operating and sleeping current;
it also provides the application with 8 additional programmable I/O pins. The device comes
in very small HVQFN32 and TSSOP28 packages, which makes it ideally suitable for
hand-held, battery-operated applications. This chip enables seamless protocol conversion
from I2C-bus/SPI to RS-232/RS-485 and is fully bidirectional.
The SC16IS762 differs from the SC16IS752 in that it supports SPI clock speeds up to
15 Mbit/s instead of the 4 Mbit/s supported by the SC16IS752, and in that it supports IrDA
SIR up to 1.152 Mbit/s. In all other aspects, the SC16IS762 is functionally and electrically
the same as the SC16IS752.
The SC16IS752/SC16IS762’s internal register set is backward compatible with the widely
used and widely popular 16C450. This allows the software to be easily written or ported
from another platform.
The SC16IS752/SC16IS762 also provides additional advanced features such as auto
hardware and software flow control, automatic RS-485 support and software reset. This
allows the software to reset the UART at any moment, independent of the hardware reset
signal.
2. Features
2.1 General features
I Dual full-duplex UART
I I2C-bus or SPI interface selectable
I 3.3 V or 2.5 V operation
I Industrial temperature range: 40 °C to +95 °C
I 64 bytes FIFO (transmitter and receiver)
I Fully compatible with industrial standard 16C450 and equivalent
I Baud rates up to 5 Mbit/s in 16× clock mode
I Auto hardware flow control using RTS/CTS
I Auto software flow control with programmable Xon/Xoff characters
I Single or double Xon/Xoff characters
I Automatic RS-485 support (automatic slave address detection)
I Up to eight programmable I/O pins
I RS-485 driver direction control via RTS signal

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SC16IS752 pdf
NXP Semiconductors
6. Pinning information
6.1 Pinning
SC16IS752/SC16IS762
Dual UART with I2C-bus/SPI interface, 64-byte FIFOs, IrDA SIR
RTSA 1
CTSA 2
TXA 3
RXA 4
RESET 5
XTAL1 6
XTAL2 7
VDD 8
I2C 9
A0 10
A1 11
n.c. 12
SCL 13
SDA 14
SC16IS752IPW
SC16IS762IPW
28 GPIO7/RIA
27 GPIO6/CDA
26 GPIO5/DTRA
25 GPIO4/DSRA
24 RXB
23 TXB
22 VSS
21 GPIO3/RIB
20 GPIO2/CDB
19 GPIO1/DTRB
18 GPIO0/DSRB
17 RTSB
16 CTSB
15 IRQ
002aab657
a. I2C-bus interface
Fig 2. Pin configuration for TSSOP28
RTSA 1
CTSA 2
TXA 3
RXA 4
RESET 5
XTAL1 6
XTAL2 7
VDD 8
SPI 9
CS 10
SI 11
SO 12
SCLK 13
VSS 14
SC16IS752IPW
SC16IS762IPW
28 GPIO7/RIA
27 GPIO6/CDA
26 GPIO5/DTRA
25 GPIO4/DSRA
24 RXB
23 TXB
22 VSS
21 GPIO3/RIB
20 GPIO2/CDB
19 GPIO1/DTRB
18 GPIO0/DSRB
17 RTSB
16 CTSB
15 IRQ
002aab599
b. SPI interface
terminal 1
index area
RXA
RESET
XTAL1
XTAL2
VDD
I2C
A0
A1
1
2
3
4
5
6
7
8
SC16IS752IBS
SC16IS762IBS
24 GPIO4/DSRA
23 RXB
22 TXB
21 VSS
20 GPIO3/RIB
19 GPIO2/CDB
18 GPIO1/DTRB
17 GPIO0/DSRB
002aab658
Transparent top view
a. I2C-bus interface
Fig 3. Pin configuration for HVQFN32
terminal 1
index area
RXA
RESET
XTAL1
XTAL2
VDD
SPI
CS
SI
1
2
3
4
5
6
7
8
SC16IS752IBS
SC16IS762IBS
24 GPIO4/DSRA
23 RXB
22 TXB
21 VSS
20 GPIO3/RIB
19 GPIO2/CDB
18 GPIO1/DTRB
17 GPIO0/DSRB
Transparent top view
b. SPI interface
002aab208
SC16IS752_SC16IS762_6
Product data sheet
Rev. 06 — 19 December 2006
© NXP B.V. 2006. All rights reserved.
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SC16IS752 arduino
NXP Semiconductors
SC16IS752/SC16IS762
Dual UART with I2C-bus/SPI interface, 64-byte FIFOs, IrDA SIR
There are two other enhanced features relating to software flow control:
Xon Any function (MCR[5]): Receiving any character will resume operation after
recognizing the Xoff character. It is possible that an Xon1 character is recognized as
an Xon Any character, which could cause an Xon2 character to be written to the
RX FIFO.
Special character (EFR[5]): Incoming data is compared to Xoff2. Detection of the
special character sets the Xoff interrupt (IIR[4]) but does not halt transmission. The
Xoff interrupt is cleared by a read of the Interrupt Identification Register (IIR). The
special character is transferred to the RX FIFO.
7.3.1 Receive flow control
When software flow control operation is enabled, the SC16IS752/SC16IS762 will
compare incoming data with Xoff1/Xoff2 programmed characters (in certain cases, Xoff1
and Xoff2 must be received sequentially). When the correct Xoff characters are received,
transmission is halted after completing transmission of the current character. Xoff
detection also sets IIR[4] (if enabled via IER[5]) and causes IRQ to go LOW.
To resume transmission, an Xon1/Xon2 character must be received (in certain cases
Xon1 and Xon2 must be received sequentially). When the correct Xon characters are
received, IIR[4] is cleared, and the Xoff interrupt disappears.
7.3.2 Transmit flow control
Xoff1/Xoff2 character is transmitted when the RX FIFO has passed the halt trigger level
programmed in TCR[3:0], or the selectable trigger level in FCR[7:6].
Xon1/Xon2 character is transmitted when the RX FIFO reaches the resume trigger level
programmed in TCR[7:4], or falls below the lower selectable trigger level in FCR[7:6].
The transmission of Xoff/Xon(s) follows the exact same protocol as transmission of an
ordinary character from the FIFO. This means that even if the word length is set to be 5, 6,
or 7 bits, then the 5, 6, or 7 least significant bits of Xoff1/Xoff2, Xon1/Xon2 will be
transmitted. (Note that the transmission of 5, 6, or 7 bits of a character is seldom done, but
this functionality is included to maintain compatibility with earlier designs.)
It is assumed that software flow control and hardware flow control will never be enabled
simultaneously. Figure 7 shows an example of software flow control.
SC16IS752_SC16IS762_6
Product data sheet
Rev. 06 — 19 December 2006
© NXP B.V. 2006. All rights reserved.
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