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PDF PCA9698 Data sheet ( Hoja de datos )
| Número de pieza | PCA9698 | |
| Descripción | 40-bit Fm+ I2C-bus advanced I/O port | |
| Fabricantes | NXP Semiconductors | |
| Logotipo |  |
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PCA9698
40-bit Fm+ I2C-bus advanced I/O port with RESET, OE and INT
Rev. 02 — 19 July 2006
Product data sheet
1. General description
The PCA9698 provides 40-bit parallel input/output (I/O) port expansion for I2C-bus
applications organized in 5 banks of 8 I/Os. At 5 V supply voltage, the outputs are capable
of sourcing 10 mA and sinking 25 mA with a total package load of 1 A to allow direct
driving of 40 LEDs. Any of the 40 I/O ports can be configured as an input or output.
The PCA9698 is the first GPIO device in a new Fast-mode Plus (Fm+) family. Fm+
devices offer higher frequency (up to 1 MHz) and longer, more densely populated bus
operation (up to 4000 pF).
The device is fully configurable: output ports can be programmed to be totem-pole or
open-drain and logic states can change at either the Acknowledge (bank change) or the
Stop Command (global change), each input port can be masked to prevent it from
generating interrupts when its state changes, I/O data logic state can be inverted when
read by the system master.
An open-drain interrupt output pin (INT) allows monitoring of the input pins and is
asserted each time a change occurs in one or several input ports (unless masked).
The Output Enable pin (OE) 3-states any I/O selected as output and can be used as an
input signal to blink or dim LEDs (PWM with frequency > 80 Hz and change duty cycle).
A ‘GPIO All Call’ command allows to program multiple Advanced GPIOs at the same time
even if they have different I2C-bus addresses. This allows optimal code programming
when more than one device needs to be programmed with the same instruction or if all
outputs need to be turned on or off at the same time (for example, LED test).
The Device ID, hard coded in the PCA9698, allows the system master to read
manufacturer, part type and revision information.
The SMBus Alert feature allows the SMBALERT pins of multiple devices with this feature
to be connected together to form a wired-AND signal and to be used in conjunction with
the SMBus Alert Response Address.
The internal Power-On Reset (POR) or hardware reset pin (RESET) initializes the 40 I/Os
as inputs. Three address select pins configure one of 64 slave addresses.
The PCA9698 is available in 56-pin TSSOP and HVQFN packages and is specified over
the −40 °C to +85 °C industrial temperature range.
2. Features
I 1 MHz Fast-mode Plus I2C-bus serial interface
I Compliant with I2C-bus Fast-mode (400 kHz) and Standard-mode (100 kHz)
1 page  
Philips Semiconductors
6. Pinning information
6.1 Pinning
PCA9698
40-bit Fm+ I2C-bus advanced I/O port with RESET, OE and INT
SDA 1
SCL 2
IO0_0 3
IO0_1 4
IO0_2 5
VSS 6
IO0_3 7
IO0_4 8
IO0_5 9
IO0_6 10
VSS 11
IO0_7 12
IO1_0 13
IO1_1 14
IO1_2 15
IO1_3 16
IO1_4 17
VDD 18
IO1_5 19
IO1_6 20
IO1_7 21
IO2_0 22
VSS 23
IO2_1 24
IO2_2 25
IO2_3 26
AD0 27
AD1 28
PCA9698DGG
Fig 3. Pin configuration for TSSOP56
56 RESET
55 INT/SMBALERT
54 IO4_7
53 IO4_6
52 IO4_5
51 VSS
50 IO4_4
49 IO4_3
48 IO4_2
47 IO4_1
46 VDD
45 IO4_0
44 IO3_7
43 IO3_6
42 IO3_5
41 IO3_4
40 IO3_3
39 VSS
38 IO3_2
37 IO3_1
36 IO3_0
35 IO2_7
34 VSS
33 IO2_6
32 IO2_5
31 IO2_4
30 OE
29 AD2
002aab932
PCA9698_2
Product data sheet
Rev. 02 — 19 July 2006
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
5 of 47
5 Page 
Philips Semiconductors
PCA9698
40-bit Fm+ I2C-bus advanced I/O port with RESET, OE and INT
7.4.1 IP0 to IP4 - Input Port registers
These registers are read-only. They reflect the incoming logic levels of the port pins
regardless of whether the pin is defined as an input or an output by the I/O Configuration
register. If the corresponding Px[y] bit in the PI registers is set to 0, or the inverted
incoming logic levels if the corresponding Px[y] bit in the PI register is set to 1. Writes to
these registers have no effect.
Table 4. IP0 to IP4 - Input Port registers (address 00h to 04h) bit description
Legend: * default value ‘X’ determined by the externally applied logic level.
Address Register
Bit
Symbol
Access Value
00h IP0
7 to 0
I0[7:0]
R
XXXX XXXX*
01h IP1
7 to 0
I1[7:0]
R
XXXX XXXX*
02h IP2
7 to 0
I2[7:0]
R
XXXX XXXX*
03h IP3
7 to 0
I3[7:0]
R
XXXX XXXX*
04h IP4
7 to 0
I4[7:0]
R
XXXX XXXX*
Description
Input Port register bank 0
Input Port register bank 1
Input Port register bank 2
Input Port register bank 3
Input Port register bank 4
The Polarity Inversion register can invert the logic states of the port pins. The polarity of
the corresponding bit is inverted when Px[y] bit in the PI register is set to 1. The polarity of
the corresponding bit is not inverted when Px[y] bits in the PI register is set to 0.
7.4.2 OP0 to OP4 - Output Port registers
These registers reflect the outgoing logic levels of the pins defined as outputs by the
I/O Configuration register. Bit values in these registers have no effect on pins defined as
inputs. In turn, reads from these registers reflect the values that are in the flip-flops
controlling the output selection, not the actual pin values.
Ox[y] = 0: IOx_y = 0 if IOx_y defined as output (Cx[y] in IOC register = 0).
Ox[y] = 1: IOx_y = 1 if IOx_y defined as output (Cx[y] in IOC register = 0).
Where ‘x’ refers to the bank number (0 to 4); ‘y’ refers to the bit number (0 to 7).
Table 5. OP0 to OP4 - Output Port registers (address 08h to 0Ch) bit description
Legend: * default value.
Address Register
Bit
Symbol
Access Value
Description
08h OP0
7 to 0
O0[7:0]
R/W
0000 0000*
Output Port register bank 0
09h OP1
7 to 0
O1[7:0]
R/W
0000 0000*
Output Port register bank 1
0Ah OP2
7 to 0
O2[7:0]
R/W
0000 0000*
Output Port register bank 2
0Bh OP3
7 to 0
O3[7:0]
R/W
0000 0000*
Output Port register bank 3
0Ch OP4
7 to 0
O4[7:0]
R/W
0000 0000*
Output Port register bank 4
PCA9698_2
Product data sheet
Rev. 02 — 19 July 2006
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
11 of 47
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