PDF AD8389 Data sheet ( Hoja de datos )

Número de pieza	AD8389
Descripción	6-Channel LCD Timing Delay-Locked Loop
Fabricantes	Analog Devices
Logotipo
Hay una vista previa y un enlace de descarga de AD8389 (archivo pdf) en la parte inferior de esta página. Total 12 Páginas
No Preview Available ! www.DataSheet4U.com Triple, 6-Channel LCD Timing Delay-Locked Loop AD8389 PRODUCT FEATURES High speed Up to 85 MHz clock rate Triple (R, G, B) output Matched delay lines Low power dissipation: 40 mW Reference to rising or falling edge of MONITI input Selectable loop delay Available in 48-lead 7 mm × 7 mm LFCSP APPLICATIONS LCD microdisplay horizontal timing PRODUCT DESCRIPTION The AD8389 is a triple 6-channel LCD microdisplay delay- locked timing loop. As part of a closed-loop system, the AD8389 maintains a constant delay between the common input, DXI, and each independent feedback reference, MONITxI. The AD8389 consists of a selectable fixed delay element, a phase detector, a charge pump, and six matched variable delay lines per color. The phase detector, charge pump, and master delay line form a closed loop when connected to a compatible LCD microdisplay. Five additional delay lines track the master for a complete set of matched timing signals. The AD8389 dissipates 40 mW nominal power. The AD8389 is offered in a 48-lead 7 mm × 7 mm LFCSP package and operates over the commercial temperature range of 0°C to 85°C. COMPEDGE SLOW DXI ENBX1I ENBX2I ENBX3I ENBX4I CLXI CLK FUNCTIONAL BLOCK DIAGRAM AVDD(4) AVSS(4) DRVDD(2) DRVSS(2) SELECTABLE DELAY PHASE DETECTOR CHARGE PUMP AD8389 MATCHED VARIABLE DELAY LINES (6-CHANNEL) 6/ /6 PHASE CHARGE DETECTOR PUMP MATCHED VARIABLE DELAY LINES (6-CHANNEL) 6/ PHASE DETECTOR CHARGE PUMP INTERNAL TIMING MATCHED VARIABLE DELAY LINES (6-CHANNEL) 6/ VCONTR MONITRI DXRO ENBX1RO ENBX2RO ENBX3RO ENBX4RO CLXRO VCONTG MONITGI DXGO ENBX1GO ENBX2GO ENBX3GO ENBX4GO CLXGO VCONTB MONITBI DXBO ENBX1BO ENBX2BO ENBX3BO ENBX4BO CLXBO Figure 1. Rev. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.326.8703 © 2003 Analog Devices, Inc. All rights reserved. 1 page PIN CONFIGURATION AND FUNCTION DESCRIPTIONS AD8389 AVSS 1 MONITRI 2 MONITGI 3 MONITBI 4 AVDD 5 AVSS 6 VCONTR 7 AVDD 8 AVSS 9 VCONTG 10 VCONTB 11 AVSS 12 PIN 1 INDICATOR AD8389 TOP VIEW (Not to Scale) 48-LEAD LFCSP 7mm × 7mm 36 DXRO 35 ENBX1RO 34 ENBX2RO 33 ENBX3RO 32 ENBX4RO 31 CLXRO 30 DXGO 29 ENBX1GO 28 ENBX2GO 27 ENBX3GO 26 ENBX4GO 25 CLXGO NC = NO CONNECT Figure 3. 48-Lead LFCSP, 7 mm × 7 mm Pin Configuration Table 3. Pin Function Descriptions Mnemonic Function AVDD, DRVDD Power Supply AVSS, DRVSS Ground CLK Clock COMPEDGE Edge Select SLOW Delay Select DXI CLXI ENBX(1–4)I MONITxI Reference Input Input Inputs Feedback Inputs DXxO CLXxO ENBX(1–4)xO VCONTx Delayed Outputs Delayed Outputs Delayed Outputs Control Voltage Description Power Supply. Ground. Clock Input. Active edge is the rising edge. When set HIGH, the phase detector compares the falling edge of DXIN with the rising edge of MONITxI. When set LOW, the phase detector compares the rising edge of DXIN with the falling edge of MONITxI. When set HIGH and COMPEDGE = HIGH, the delay between the falling edges of DXI and the rising edges of MONITI is maintained at 9/(fCLK) + t4. The delay is maintained at 26/(fCLK) + t4 when COMPEDGE = LOW. When set LOW and COMPEDGE = HIGH, the delay between the falling edges of DXI and the rising edges of MONITI is maintained at 15/(fCLK) + t4. The delay is maintained at 32/(fCLK) + t4 with COMPEDGE = LOW. LCD Timing Input from the Image Processor. Used as the input to all phase detectors. LCD Timing Input from the Image Processor. LCD Timing Inputs from the Image Processor. Inputs from the LCD. Used as the feedback input to each phase detector. When the AD8389 forms part of a closed loop, it maintains a constant delay between the DXI input and this reference input pin. 200 pF capacitors connected between these pins and the AVSS plane are required for proper operation of the internal charge pump. Rev. 0 \| Page 5 of 12 5 Page NOTES AD8389 Rev. 0 \| Page 11 of 12 11 Page

Páginas	Total 12 Páginas
PDF Descargar	[ Datasheet AD8389.PDF ]

Hoja de datos destacado

Número de pieza	Descripción	Fabricantes
AD8380	Decimating LCD Panel Driver	Analog Devices
AD8381	6-Channel Output DecDriver Decimating LCD Panel Driver	Analog Devices
AD8382	Decimating LCD DecDriver	Analog Devices
AD8383	6-Channel Output Decimating LCD	Analog Devices

Número de pieza	Descripción	Fabricantes
SLA6805M	High Voltage 3 phase Motor Driver IC.	Sanken
SDC1742	12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters.	Analog Devices

DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares,
permitiéndote verlos en linea o descargarlos en PDF.

DataSheet.es | 2020 | Privacy Policy | Contacto | Buscar