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PDF FS6128-04 Data sheet ( Hoja de datos )

Número de pieza FS6128-04
Descripción (FS6128-04-05-06) PLL Clock Generator IC
Fabricantes AMI 
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AMERICAN MICROSYSTEMS, INC.
FS6128-04 / FS6128-05 / FS6128-06
PLL Clock Generator IC with VCXO
April 2000
1.0 Features
Phase-locked loop (PLL) device synthesizes output
clock frequency from crystal oscillator or external ref-
erence clock
On-chip tunable voltage-controlled crystal oscillator
(VCXO) allows precise system frequency tuning
Typically used for generation of MPEG-2 decoder
clock
3.3V supply voltage
Very low phase noise PLL
Use with “pullable” 14pF crystals – no external pad-
ding capacitors required
Small circuit board footprint (8-pin 0.150SOIC)
Custom frequency selections available - contact your
local AMI Sales Representative for more information
2.0 Description
The FS6128 is a monolithic CMOS clock generator IC
designed to minimize cost and component count in digital
video/audio systems.
At the core of the FS6128 is circuitry that implements a
voltage-controlled crystal oscillator (VCXO) when an ex-
ternal resonator (nominally 13.5MHz) is attached. The
VCXO allows device frequencies to be precisely adjusted
for use in systems that have frequency matching re-
quirements, such as digital satellite receivers.
A high-resolution phase-locked loop generates an output
clock (CLK) through a post-divider. The CLK frequency is
ratiometrically derived from the VCXO frequency. The
locking of the CLK frequency to other system reference
frequencies can eliminate unpredictable artifacts in video
systems and reduce electromagnetic interference (EMI)
due to frequency harmonic stacking.
Figure 1: Pin Configuration
XIN 1
VDD 2
XTUNE 3
VSS 4
8 XOUT
7 VSS
6 n/c
5 CLK
8-pin (0.150) SOIC
Table 1: Crystal / Output Frequencies
DEVICE
fXIN (MHz)
FS6128-04
13.500
FS6128-05
13.500
FS6128-06
13.500
NOTE: Contact AMI for custom PLL frequencies
CLK (MHz)
27.000
13.500
54.000
Figure 2: Block Diagram
XIN
XOUT
VCXO
PLL
DIVIDER
CLK
XTUNE
FS6128-04
FS6128-05
FS6128-06
American Microsystems, Inc. reserves the right to change the detail specifications as may be required to permit improvements in the design of its products.
ISO9001
4.24.00

1 page




FS6128-04 pdf
AMERICAN MICROSYSTEMS, INC.
FS6128-04 / FS6128-05 / FS6128-06
PLL Clock Generator IC with VCXO
April 2000
Table 6: AC Timing Specifications
Unless otherwise stated, VDD = 3.3V ± 10%, no load on any output, and ambient temperature range TA = 0°C to 70°C. Parameters denoted with an asterisk ( * ) represent nominal characterization
data and are not production tested to any specific limits. Where given, MIN and MAX characterization data are ± 3σ f rom typical.
PARAMETER
SYMBOL
CONDITIONS/DESCRIPTION
MIN. TYP. MAX. UNITS
Overall
VCXO Stabilization Time *
PLL Stabilization Time *
Synthesis Error
Clock Output (CLK)
Duty Cycle *
Jitter, Period (peak-peak) *
Jitter, Long Term (σy(τ )) *
Rise Time *
Fall Time *
tVCXOSTB
tPLLSTB
From power valid
From VCXO stable
(unless otherwise noted in Frequency Table)
10 ms
100 us
0 ppm
Ratio of high pulse width (as measured from rising
edge to next falling edge at VDD/2) to one clock period
45
55
tj(P)
From rising edge to next rising edge at VDD/2, CL =
10pF
200
tj(LT)
From 0-500µs at VDD/2, CL = 10pF
compared to ideal clock source
100
tr VDD = 3.3V; VO = 0.3V to 3.0V; CL = 10pF
1.7
tf VDD = 3.3V; VO = 3.0V to 0.3V; CL = 10pF
1.7
%
ps
ps
ns
ns
ISO9001
5
4.24.00

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