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PDF NCP1271 Data sheet ( Hoja de datos )
| Número de pieza | NCP1271 | |
| Descripción | Soft Skip Mode Standby PWM Controller | |
| Fabricantes | ON Semiconductor | |
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NCP1271
Soft-Skipt Mode Standby
PWM Controller with
Adjustable Skip Level and
External Latch
The NCP1271 represents a new, pin to pin compatible, generation
of the successful 7−pin current mode NCP12XX product series. The
controller allows for excellent stand by power consumption by use of
its adjustable Soft−Skip mode and integrated high voltage startup
FET. This proprietary Soft−Skip also dramatically reduces the risk of
acoustic noise. This allows the use of inexpensive transformers and
capacitors in the clamping network. Internal frequency jittering,
ramp compensation, timer−based fault detection and a latch input
make this controller an excellent candidate for converters where
ruggedness and component cost are the key constraints.
Features
• Fixed−Frequency Current−Mode Operation with Ramp
Compensation and Skip Cycle in Standby Condition
• Timer−Based Fault Protection for Improved Overload Detection
• “Soft−Skip Mode” Technique for Optimal Noise Control in Standby
• Internal High−Voltage Startup Current Source for Lossless Startup
• "5% Current Limit Accuracy over the Full Temperature Range
• Adjustable Skip Level
• Internal Latch for Easy Implementation of Overvoltage and
Overtemperature Protection
• Frequency Jittering for Softened EMI Signature
• +500 mA/−800 mA Peak Current Drive Capability
• Sub−100 mW Standby Power can be Achieved
• Pin−to−Pin Compatible with the Existing NCP120X Series
• This is a Pb−Free Device
Typical Applications
• AC−DC Adapters for Notebooks, LCD Monitors
• Offline Battery Chargers
• Consumer Electronic Appliances STB, DVD, DVDR
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SOIC−7
D SUFFIX
CASE 751U
MARKING
DIAGRAMS
8
1271x
ALYWG
G
1
8
1
PDIP−7 VHVIC
P SUFFIX
CASE 626B
1
1271Pxxx
AWL
YYWWG
x = A or B
A= 65 kHz
B= 100 kHz
xxx = Device Code: 65, 100
A = Assembly Location
L, WL = Wafer Lot
Y, YY = Year
W, WW = Work Week
G or G = Pb−Free Package
(Note: Microdot may be in either location)
PIN CONNECTIONS
Skip/latch 1
FB 2
CS 3
GND 4
8 HV
6 VCC
5 Drv
(Top View)
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 19 of this data sheet.
*For additional information on our Pb−Free strategy and soldering details, please
download the ON Semiconductor Soldering and Mounting Techniques Reference
Manual, SOLDERRM/D.
© Semiconductor Components Industries, LLC, 2009
September, 2009 − Rev. 6
1
Publication Order Number:
NCP1271/D
1 page  
NCP1271
ELECTRICAL CHARACTERISTICS (For typical values TJ = 25°C, for min/max values, TJ = −40°C to +125°C, VCC = 14 V,
HV = open, skip = open, FB = 2 V, CS = Ground, DRV = 1 nF, unless otherwise noted.)
Characteristic
Pin Symbol Min Typ Max
OSCILLATOR
Oscillation Frequency (65 kHz Version, TJ = 25_C)
Oscillation Frequency (65 kHz Version, TJ = −40 to + 85_C)
Oscillation Frequency (65 kHz Version, TJ = −40 to + 125_C)
Oscillation Frequency (100 kHz Version, TJ = 25_C)
Oscillation Frequency (100 kHz Version, TJ = −40 to +85_C)
Oscillation Frequency (100 kHz Version, TJ = −40 to +125_C)
Oscillator Modulation Swing, in Percentage of fosc
Oscillator Modulation Swing Period
5 fosc 61.75 65 68.25
58 65 69
55 65 69
95 100 105
89 100 107
85 100 107
5
−
−
"7.5
−
5 − − 6.0 −
Maximum Duty Cycle (VCS = 0 V, VFB = 2.0 V)
GATE DRIVE
Gate Drive Resistance
Output High (VCC = 14 V, Drv = 300 W to Gnd)
Output Low (VCC = 14 V, Drv = 1.0 V)
Rise Time from 10% to 90% (Drv = 1.0 nF to Gnd)
Fall Time from 90% to 10% (Drv = 1.0 nF to Gnd)
CURRENT SENSE
Maximum Current Threshold
Soft−Start Duration
Soft−Skip Duration
Leading Edge Blanking Duration
Propagation Delay (Drv =1.0 nF to Gnd)
Ramp Current Source Peak
Ramp Current Source Valley
SKIP
Default Standby Skip Threshold (Pin 1 = Open)
Skip Current (Pin 1 = 0 V, TJ = 25_C)
Skip Level Reset (Note 5)
Transient Load Detection Level to Disable Soft−Skip Mode
EXTERNAL LATCH
Latch Protection Threshold
Latch Threshold Margin (Vlatch−m = VCC(off) − Vlatch)
Noise Filtering Duration
5
Dmax
75 80 85
5
ROH
ROL
6.0 11 20
2.0 6.0 12
5 tr − 30 −
5 tf − 20 −
3
ILimit
0.95 1.0 1.05
− tSS − 4.0 −
− tSK − 300 −
3 tLEB 100 180 330
− − − 50 150
3 Iramp(H) − 100 −
3 Iramp(L) − 0 −
2 Vskip − 1.2 −
1 Iskip 26 43 56
1
Vskip−reset
5.0 5.7 6.5
2
VTLD
2.6 2.85 3.15
1
Vlatch
7.1 8.0 8.7
1
Vlatch−m
0.6 1.2
−
1 − − 13 −
Propagation Delay (Drv = 1.0 nF to Gnd)
SHORT−CIRCUIT FAULT PROTECTION
Time for Validating Short−Circuit Fault Condition
5. Please refer to Figure 39 for detailed description.
6. Guaranteed by design.
1 Tlatch − 100 −
2 tprotect − 130 −
Unit
kHz
%
ms
%
W
ns
ns
V
ms
ms
ns
ns
mA
mA
V
mA
V
V
V
V
ms
ns
ms
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5
5 Page 
NCP1271
cleared after the double hiccup, then the application
restarts. If not, then the process is repeated.
4. Latched Shutdown – When the Skip/latch pin (Pin
1) voltage is pulled above 8.0 V for more than
13 ms, the NCP1271 goes into latchoff shutdown.
The output is held low and VCC stays in hiccup
mode until the latch is reset. The reset can only
occur if Vcc is allowed to fall below VCC(reset)
(4.0 V typical). This is generally accomplished by
unplugging the main input AC source.
5. Non−Latched Shutdown – If the FB pin is pulled
below the skip level, then the device will enter a
non−latched shutdown mode. This mode disables
the driver, but the controller automatically recovers
when the pulldown on FB is released. Alternatively,
Vcc can also be pulled low (below 190 mV) to
shutdown the controller. This has the added benefit
of placing the part into a low current consumption
mode for improved power savings.
Biasing the Controller
During startup, the Vcc bias voltage is supplied by the
HV Pin (Pin 8). This pin is capable of supporting up to
500 V, so it can be connected directly to the bulk capacitor.
Internally, the pin connects to a current source which
rapidly charges VCC to its VCC(on) threshold. After this
level is reached, the controller turns on and the transformer
auxiliary winding delivers the bias supply voltage to VCC.
The startup FET is then turned off, allowing the standby
power loss to be minimized. This in−chip startup circuit
minimizes the number of external components and Printed
Circuit Board (PCB) area. It also provides much lower
power dissipation and faster startup times when compared
to using startup resistors to VCC. The auxiliary winding
needs to be designed to supply a voltage above the VCC(off)
level but below the maximum VCC level of 20 V.
For added protection, the NCP1271 also include a dual
startup mode. Initially, when VCC is below the inhibit
voltage Vinhibit (600 mV typical), the startup current source
is small (200 uA typical). The current goes higher (4.1 mA
typical) when VCC goes above Vinhibit. This behavior is
illustrated in Figure 23. The dual startup feature protects
the device by limiting the maximum power dissipation
when the VCC pin (Pin 6) is accidentally grounded. This
slightly increases the total time to charge VCC, but it is
generally not noticeable.
Startup current
4.1 mA
200 uA
0.6 V
VCC(latch)
VCC(on) VCC
Figure 23. Startup Current at Various VCC Levels
VCC Double Hiccup Mode
Figure 24 illustrates the block diagram of the startup
circuit. An undervoltage lockout (UVLO) comparator
monitors the VCC supply voltage. If VCC falls below
VCC(off), then the controller enters “double hiccup mode.”
Vbulk
4.1 mA when Vcc > 0.6 V
200 uA when Vcc < 0.6 V
turn off
QS
R
double
hiccup
B2
Counter
&
UVLO
+
−
12.6/
5.8 V
9.1 V
−
+
20V
HV
8
Vcc
6
turn on internal bias
Figure 24. VCC Management
During double hiccup operation, the Vcc level falls to
VCC(latch) (5.8 V typical). At this point, the startup FET is
turned back on and charges VCC to VCC(on) (12.6 V typical).
VCC then slowly collapses back to the VCC(latch) level. This
cycle is repeated twice to minimize power dissipation in
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| Páginas | Total 21 Páginas | |
| PDF Descargar | [ Datasheet NCP1271.PDF ] | |
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