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PDF ADUC7032 Data sheet ( Hoja de datos )
| Número de pieza | ADUC7032 | |
| Descripción | Precision Battery Sensor | |
| Fabricantes | Analog Devices | |
| Logotipo |  |
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Preliminary Technical Data
MicroConverter® Integrated,
Precision Battery Sensor
ADuC7032
FEATURES
High Precision ADCs
Dual Channel, Simultaneous Sampling, 16-Bit Σ−∆ ADCs
Third Independent ADC for Temperature Sensing
Programmable ADC throughput from 1Hz to 8KHz
On-Chip 5ppm/°C Voltage Reference
Current Channel
Fully differential, Buffered Input
Programmable Gain 1 to 512
ADC Input Range -200mV to +300mV
Digital Comparators, with Current Accumulator Feature
Voltage Channel
Buffered, On-Chip attenuator for 12V battery Inputs
Temperature Channel
External and On-Chip Temperature Sensor Options
Microcontroller
ARM7TDMI Core, 16/32-bit RISC architecture
20.48MHz PLL with Programmable Divider
PLL Input Source: On-Chip Precision Oscillator
On-Chip Low-Power Oscillator
External (32.768KHz) Watch Crystal
JTAG Port supports code download and debug
Memory
96k Bytes Flash/EE Memory, 6k Bytes SRAM
10KCycles Flash Endurance, 20 Years Flash Retention
In-Circuit Download via JTAG and LIN
64 x 16bit Result FIFO for Current and Voltage ADC
On-Chip Peripherals
LIN 1.2, 1.3 and 2.0 (Slave) Compatible Support via UART
with Hardware Synchronization
Flexible Wake-up I/O Pin, Master/Slave SPI Serial I/O
9-Pin GPIO Port, 2 X General Purpose Timers
Wake-up and Watchdog Timers
Power Supply Monitor, On-Chip Power-On-Reset
Power
Operates directly from 12V Battery Supply
Current Consumption
Normal Mode 10mA at 10MHz
Low Power Monitor Mode
Package and Temperature Range
48 Pin LQFP 7X7 mm body package
Fully specified for –40°C to 105°C operation
APPLICATIONS
Battery Sensing/Management for Automotive Systems
FUNCTIONAL BLOCK DIAGRAM
IIN+
IIN-
VBAT
VTEMP
GND_SW
VREF
PRECISION ANALOG ACQUISITION
BUF PGA
16-BIT
Σ−∆ ADC
RESULT
DIGITAL
ACCUMULATOR COMPARATOR
BUF
16-BIT
Σ−∆ ADC
MUX BUF
16-BIT
Σ−∆ ADC
TEMP
SENSOR
PRECISION
REFERENCE
2.5V LDO
PSM
POR
MEMORY
96KB FLASH
6KB RAM
128B ADC FIFO
RESET
ARM7TDMI
MCU
20MHz
PRECISION
OSC
LOW POWER
OSC
ON-CHIP PLL
XTAL1
XTAL2
2xTIMERS
WDT
W/U TIMER
GPIO PORT
UART PORT
SPI PORT
LIN
WU
LIN
Figure 1: ADuC7032 Functional Block Diagram
Rev. PrD
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Preliminary Specifications subject to change without notice. No license is granted by
implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective
companies.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.326.8703 © 2006 Analog Devices, Inc. All rights reserved.
1 page  
Preliminary Technical Data
ADUC7032 DATASHEET TABLES
ADuC7032
Table 1 : ADUC7032—SPECIFICATIONS
8
Table 2 : SPI Master Mode Timing (PHASE Mode = 1)
15
Table 3 : SPI Master Mode Timing (PHASE Mode = 0)
16
Table 4 : SPI Slave Mode Timing (PHASE Mode = 1)
17
Table 5 : SPI Slave Mode Timing (PHASE Mode = 0)
18
Table 6. Absolute Maximum Ratings (TA = -40°C to 105°C
unless otherwise noted)
22
Table 7: Pin Function Descriptions
23
Table 8: SYSMAP0 MMR Bit Designations
29
Table 9 : Device RESET Implications
30
Table 10: RSTSTA/RSTCLR MMR Bit Designations
30
Table 11: Command Codes in FEE0CON and FEE1CON 32
Table 12: FEE0STA and FEE1STA MMR bit designations 33
Table 13: FEE0MOD and FEE1MOD MMR bit designations 34
Table 14: FEE0HID and FEE0PRO MMR bit designations 35
Table 15: FEE1HID and FEE1PRO MMR bit designations 35
Table 16: Typical execution cycles in ARM/Thumb mode 37
Table 17 : Complete MMR List
41
Table 18 : GND_SW Configuration
47
Table 19 : Current Channel ADC, Normal Power Mode, Typical
Output RMS Noise (µV)
48
Table 20 : Voltage Channel ADC, Typical Output RMS Noise
(referred to ADC Voltage attenuator Input)(µV)
48
Table 21 : Temperature Channel ADC, Typical Output RMS
Noise (µV)
48
Table 22 : ADCSTA MMR Bit Designations
49
Table 23 : ADCMDE MMR Bit Designations
51
Table 24 : ADC0CON MMR Bit Designations
52
Table 25 : ADC1CON MMR Bit Designations
53
Table 26 : ADC2CON MMR Bit Designations
54
Table 27 : ADCFLT MMR Bit Designations
55
Table 28 : ADC Conversion Rates and Settling Times
56
Table 29 : Allowable Combinations of SF and AF
Table 30: ADCCFG MMR Bit Designations
Table 31 : Allowable Combinations of SF and AF
Table 32 : Common ADCFLT Configurations
Table 33: Current ADC Diagnostics
Table 34: Temperature ADC Diagnostics
Table 35 : PLLSTA MMR Bit Description
Table 36: PLLCON MMR Bit description
Table 37 : POWCON MMR bit designations
Table 38 : OSC0TRM MMR Bit Definition
Table 39: OSC0CON MMR Bit Definition
Table 40 : OSC0STA MMR Bit Definition
Table 41 : IRQ/FIQ MMRs bit description
Table 42 : SWICFG MMR Bit Descriptions
Table 43 : Timer Event Capture
Table 44 : T0CON MMR Bit Descriptions
Table 45 : T1CON MMR Bit Descriptions
Table 46 : T2CON MMR Bit Descriptions
Table 47 : T3CON MMR Bit Definition
Table 48 : External GPIO Pin to Internal Port Signal
Assignments
Table 49 : GP0CON MMR Bit Designations
Table 50 : GP1CON MMR Bit Designations
Table 51 : GP2CON MMR Bit Designations
Table 52 : GP0DAT MMR Bit Descriptions
Table 53 : GP1DAT MMR Bit Descriptions
Table 54 :GP2DAT MMR Bit Descriptions
Table 55 : GP0SET MMR Bit Descriptions
Table 56 : GP1SET MMR Bit Descriptions
Table 57 : GP2SET MMR Bit Descriptions
Table 58 : GP0CLR MMR Bit Descriptions
Rev. PrD | Page 5 of 128
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5 Page 
Preliminary Technical Data
Parameter
LOGIC INPUTS 1
VINL, Input Low Voltage
VINH, Input High Voltage
CRYSTAL OSCILLATOR1
Logic Inputs, XTAL1 Only
VINL, Input Low Voltage
VINH, Input High Voltage
XTAL1 Capacitance
XTAL2 Capacitance
ON-CHIP OSCILLATORS
Low Power Oscillator
Accuracy30
Precision Oscillator
Accuracy
MCU CLOCK RATE
MCU START-UP TIME
at Power-On
after Reset Event
From MCU Power-Down
Oscillator Running
Wakeup from Interrupt
Wakeup from LIN
Crystal Powered Down
Wakeup from Interrupt
Internal PLL Lock Time
LIN I/O General
Baud Rate
VDD
Input capacitance
LIN comparator response
timeError! Bookmark not defined.
ILIN DOM MAX
ILIN_PAS_REC
ILIN_PAS_DOM1
Test Conditions/Comments
All Logic inputs
Min
2.0
1.7
Includes drift data from 1000hr life-test
-6
Includes drift data from 1000hr life-test
-1.2
8 programmable core clock selections within
this range (binary divisions 1,2,4,8…..64, 128)
0.160
Includes kernel power-on execution time
Includes kernel power-on execution time
Supply Voltage Range for which the LIN
interface is functional
Using 22Ohm resistor
Current Limit for driver when LIN Bus is in
dominant state. VBAT = VBAT (MAX)
Driver Off ; 7.0V < VBUS < 18V ; VDD = VLIN -0.7V
Input Leakage VLIN = 0V
1000
7
40
-1
Rev. PrD | Page 11 of 128
ADuC7032
Typ Max Unit
0.4 V
V
0.8 V
V
12 pF
12 pF
131.072
131.072
10.24
kHz
3%
kHz
1.2 %
20.48 MHz
25 msec
5 msec
2 msec
2 msec
500 msec
1 msec
20000 Bits/sec
18 V
5.5 pF
38 90 µs
200 mA
20 µA
mA
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet ADUC7032.PDF ] | |
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