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PDF ADT7475 Data sheet ( Hoja de datos )
| Número de pieza | ADT7475 | |
| Descripción | dBCool Remote Thermal Monitor and Fan Controller | |
| Fabricantes | Analog Devices | |
| Logotipo |  |
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dBCool® Remote Thermal
Monitor and Fan Controller
ADT7475
FEATURES
GENERAL DESCRIPTION
Controls and monitors up to 4 fans
High and low frequency fan drive signal
1 on-chip and 2 remote temperature sensors
Extended temperature measurement range, up to 191°C
Automatic fan speed control mode controls system cooling
based on measured temperature
Enhanced acoustic mode dramatically reduces user
perception of changing fan speeds
Thermal protection feature via THERM output
The ADT7475 dBCool controller is a thermal monitor and
multiple PWM fan controller for noise-sensitive or power-
sensitive applications requiring active system cooling. The
ADT7475 can drive a fan using either a low or high frequency
drive signal, monitor the temperature of up to two remote
sensor diodes plus its own internal temperature, and measure
and control the speed of up to four fans, so they operate at the
lowest possible speed for minimum acoustic noise.
Monitors performance impact of Intel® Pentium® 4 processor
The automatic fan speed control loop optimizes fan speed
Thermal control circuit via THERM input
for a given temperature. The effectiveness of the system’s
3-wire and 4-wire fan speed measurement
thermal solution can be monitored using the THERM input.
Limit comparison of all monitored values
The ADT7475 also provides critical thermal protection to the
Meets SMBus 2.0 electrical specifications
(fully SMBus 1.1 compliant)
Fully RoHS compliant
system using the bidirectional THERM pin as an output to
prevent system or component overheating.
FUNCTIONAL BLOCK DIAGRAM
SCL SDA SMBALERT
PWM1
PWM2
PWM3
TACH1
TACH2
TACH3
TACH4
THERM
VCC
D1+
D1–
D2+
D2–
VCCP
ADT7475
SERIAL BUS
INTERFACE
PWM
REGISTERS
AND
CONTROLLERS
(HF AND LF)
ACOUSTIC
ENHANCEMENT
CONTROL
AUTOMATIC
FAN SPEED
CONTROL
VCC TO ADT7475
FAN
SPEED
COUNTER
PERFORMANCE
MONITORING
THERMAL
PROTECTION
ADDRESS
POINTER
REGISTER
PWM
CONFIGURATION
REGISTERS
INTERRUPT
MASKING
INTERRUPT
STATUS
REGISTERS
BAND GAP
TEMPERATURE
SENSOR
INPUT
SIGNAL
CONDITIONING
AND
ANALOG
MULTIPLEXER
10-BIT
ADC
BAND GAP
REFERENCE
GND
Figure 1.
LIMIT
COMPARATORS
VALUE AND
LIMIT
REGISTERS
Rev. A
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
©2006 Analog Devices, Inc. All rights reserved.
1 page  
ABSOLUTE MAXIMUM RATINGS
Table 2.
Parameter
Rating
Positive Supply Voltage (VCC)
Voltage on Any Input or Output Pin
3.6 V
−0.3 V to +3.6 V
Input Current at Any Pin
±5 mA
Package Input Current
±20 mA
Maximum Junction Temperature (TJMAX)
Storage Temperature Range
150°C
−65°C to +150°C
Lead Temperature, Soldering
IR Reflow Peak Temperature
260°C
Lead Temperature (Soldering 10 sec)
300°C
ESD rating
1500 V
ADT7475
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
THERMAL CHARACTERISTICS
16-lead QSOP package:
θJA = 150°C/W
θJC = 39°C/W
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
Rev. A | Page 5 of 68
5 Page 
ADT7475
SCL
1
91
9
SDA
START BY
MASTER
0
SCL
1
1 011 1 0
FRAME 1
SERIAL BUS ADDRESS BYTE
R/W D7
ACK. BY
ADT7475
D6 D5 D4 D3 D2 D1 D0
FRAME 2
ADDRESS POINTER REGISTER BYTE
ACK. BY
ADT7475
STOP BY
MASTER
Figure 15. Writing to the Address Pointer Register Only
91
9
SDA
START BY
MASTER
0
1 0 1 1 1 0 R/W
D7 D6 D5 D4 D3 D2 D1
FRAME 1
SERIAL BUS ADDRESS BYTE
ACK. BY
ADT7475
FRAME 2
DATA BYTE FROM ADT745
Figure 16. Reading Data from a Previously Selected Register
D0
NO ACK. BY STOP BY
MASTER MASTER
It is possible to read a data byte from a data register without
first writing to the address pointer register, if the address
pointer register is already at the correct value. However, it is
not possible to write data to a register without writing to the
address pointer register, because the first data byte of a write
is always written to the address pointer register.
In addition to supporting the send byte and receive byte pro-
tocols, the ADT7475 also supports the read byte protocol.
(See System Management Bus Specifications Rev. 2.0 for more
information; this document is available from Intel.)
If several read or write operations must be performed in
succession, the master can send a repeat start condition
instead of a stop condition to begin a new operation.
WRITE OPERATIONS
The SMBus specification defines several protocols for differ-
ent types of read and write operations. The ones used in the
ADT7475 are discussed in this section. The following
abbreviations are used in the diagrams:
S—START
P—STOP
R—READ
W—WRITE
A—ACKNOWLEDGE
A—NO ACKNOWLEDGE
The ADT7475 uses the following SMBus write protocols.
Send Byte
In this operation, the master device sends a single command
byte to a slave device as follows:
1. The master device asserts a start condition on SDA.
2. The master sends the 7-bit slave address followed by
the write bit (low).
3. The addressed slave device asserts ACK on SDA.
4. The master sends a command code.
5. The slave asserts ACK on SDA.
6. The master asserts a stop condition on SDA and the
transaction ends.
For the ADT7475, the send byte protocol is used to write a
register address to RAM for a subsequent single byte read from
the same address. This operation is shown in Figure 17.
12
3 4 56
S
SLAVE
ADDRESS
W
A
REGISTER
ADDRESS
AP
Figure 17. Setting a Register Address for a Subsequent Read
If the master is required to read data from the register immedi-
ately after setting up the address, it can assert a repeat start
condition immediately after the final ACK and carry out a
single byte read without asserting an intermediate stop
condition.
Write Byte
In this operation, the master device sends a command byte and
one data byte to the slave device as follows:
1. The master device asserts a start condition on SDA.
2. The master sends the 7-bit slave address followed by the
write bit (low).
3. The addressed slave device asserts ACK on SDA.
4. The master sends a command code.
5. The slave asserts ACK on SDA.
6. The master sends a data byte.
7. The slave asserts ACK on SDA.
8. The master asserts a stop condition on SDA and the
transaction ends.
Rev. A | Page 11 of 68
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet ADT7475.PDF ] | |
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