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Analog Devices - Blackfin Embedded Processor

Numéro de référence ADSP-BF539
Description Blackfin Embedded Processor
Fabricant Analog Devices 
Logo Analog Devices 





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Preliminary Technical Data
FEATURES
1.0 V to 1.2 V core VDD with on-chip voltage regulation
3.3 V tolerant I/O with specific 5 V tolerant pins
316-ball Pb-free mini-BGA package
Up to 500 MHz high performance Blackfin processor
Two 16-bit MACs, two 40-bit ALUs, four 8-bit video ALUs,
40-bit shifter
RISC-like register and instruction model for ease of
programming and compiler friendly support
Advanced debug, trace, and performance monitoring
MEMORY
148K bytes of on-chip memory:
16K bytes of instruction SRAM/cache
64K bytes of instruction SRAM
32K bytes of data SRAM
32K bytes of data SRAM/cache
4K bytes of scratchpad SRAM
512K x 16-bits or 256K x 16-bits of flash memory
(ADSP-BF539F only)
Four dual-channel memory DMA controllers
Memory management unit providing memory protection
Blackfin®
Embedded Processor
ADSP-BF539/ADSP-BF539F
External memory controller with glueless support
for SDRAM, SRAM, flash, and ROM
Flexible memory booting options from SPI®, external
memory
PERIPHERALS
Parallel peripheral interface (PPI),
supporting ITU-R 656 video data formats
Four dual-channel, full-duplex synchronous serial ports, sup-
porting 16 stereo I2S® channels
Two DMA controllers supporting 26 channels
Controller area network (CAN) 2.0B controller
Media transceiver (MXVR) for connection
to a MOST® network
Three SPI-compatible ports
Three timer/counters with PWM support
Three UARTs with support for IrDA®
Two TWI controllers compatible with I2C® industry standard
38 general purpose I/O pins (GPIO)
16 general purpose flag pins (GPF)
Real time clock
Watchdog timer
Debug/JTAG interface
On-chip PLL capable of 0.5x To 64x frequency multiplication
GPIO
PORT
C
GPIO
PORT
D
GPIO
PORT
E
TWI0-1
CAN 2.0B
MXVR
SPI1-2
UART1-2
SPORT2-3
VOLTAGE REGULATOR
JTAG TEST AND EMULATION
PERIPHERAL ACCESS BUS
B
INTERRUPT
CONTROLLER
DMA CORE
BUS 3
DMA
CONTROLLER1
L1
INSTRUCTION
MEMORY
L1
DATA
MEMORY
DMA
CONTROLLER0
DMA CORE
BUS 1
DMA
EXTERNAL
BUS 1
DMA CORE BUS 0
DMA
EXTERNAL
BUS 0
EXTERNAL PORT
FLASH, SDRAM CONTROL
WATCHDOG
TIMER
RTC
PPI
TIM ER 0- 2
SPI0
UART0
SPORT0-1
GPIO
PORT
F
512 KB OR 1 MB
FLASH MEMORY
(ADSP-BF539F ONLY)
BOOT ROM
Figure 1. Functional Block Diagram
Blackfin and the Blackfin logo are registered trademarks of Analog Devices, Inc.
Rev. PrF
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106 U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113 © 2006 Analog Devices, Inc. All rights reserved.

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