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PDF ADP3186 Data sheet ( Hoja de datos )
| Número de pieza | ADP3186 | |
| Descripción | 5-Bit Programmable 2-/3-/4-Phase Synchronous Buck Controller | |
| Fabricantes | Analog Devices | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de ADP3186 (archivo pdf) en la parte inferior de esta página. Total 24 Páginas | ||
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5-Bit Programmable 2-/3-/4-Phase
Synchronous Buck Controller
ADP3186
FEATURES
Selectable 2-, 3-, or 4-phase operation at up to 1 MHz
per phase
±1% worst-case differential sensing error over temperature
Logic-level PWM outputs for interface to external high
power drivers
Active current balancing between all output phases
Built-in power good/crowbar blanking supports on-the-fly
VID code changes
5-bit digitally programmable 0.8 V to 1.55 V output
Programmable short-circuit protection with programmable
latch-off delay
APPLICATIONS
Desktop PC power supplies for
AMD Opteron™ processors
VRM modules
GENERAL DESCRIPTION
The ADP3186 is a highly efficient multiphase synchronous
buck switching regulator controller optimized for converting a
12 V main supply into the core supply voltage required by high
performance AMD processors. It uses an internal 5-bit DAC to
read a voltage identification (VID) code directly from the pro-
cessor, which is used to set the output voltage between 0.8 V
and 1.55 V. It uses a multimode PWM architecture to drive the
logic-level outputs at a programmable switching frequency that
can be optimized for VR size and efficiency. The phase relation-
ship of the output signals can be programmed to provide 2-, 3-,
or 4-phase operation, allowing the construction of up to four
complementary buck switching stages.
The ADP3186 includes programmable no-load offset and slope
functions to adjust the output voltage as a function of the load
current, so that it is always optimally positioned for a system
transient. The ADP3186 also provides accurate and reliable
short-circuit protection, adjustable current limiting, and a power
good output that accommodates on-the-fly output voltage
changes requested by the CPU.
The ADP3186 is specified over the commercial temperature
range of 0°C to 85°C and is available in 28-lead TSSOP and
QSOP packages.
FUNCTIONAL BLOCK DIAGRAM
VCC
28
ADP3186
RAMPADJ RT
14 13
EN 11
GND 19
UVLO
SHUTDOWN
AND BIAS
OSCILLATOR
CMP
SET
RESET
EN
27 PWM1
CROWBAR 6
CSREF
2.1V
DAC + 300mV
CSREF
DAC – 300mV
PWRGD 10
DELAY
ILIMIT 15
EN
DELAY 12
COMP 9
SOFT
START
CURRENT
BALANCING
CIRCUIT
CMP
CMP
RESET
2-/3-/4-PHASE
DRIVER LOGIC
RESET
26 PWM2
25 PWM3
CMP RESET
24 PWM4
CROWBAR
CURRENT
LIMIT
CURRENT
LIMIT
CIRCUIT
23 SW1
22 SW2
21 SW3
20 SW4
17 CSSUM
16 CSREF
18 CSCOMP
8 FB
PRECISION
REFERENCE
VID
DAC
7
FBRTN
1
VID4
2
VID3
3
VID2
4
VID1
5
VID0
Figure 1.
Rev. A
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
©2006 Analog Devices, Inc. All rights reserved.
1 page  
TEST CIRCUITS
5-BIT CODE
1k Ω
1.25V
4.7nF 250kΩ
ADP3186
1 VID4
VCC 28
2 VID3
PWM1 27
+1μF
3 VID2
PWM2 26
4 VID1
PWM3 25
5 VID0
PWM4 24
6 CROWBAR SW1 23
7 FBRTN
SW2 22
8 FB
SW3 21
9 COMP
SW4 20
10 PWRGD
GND 19
11 EN
12 DELAY
CSCOMP 18
20kΩ
CSSUM 17
13 RT
CSREF 16
14 RAMPADJ
ILIMIT 15
250kΩ
12V
100n F
100nF
Figure 2. Closed-Loop Output Voltage Accuracy
12V
39kΩ
1kΩ
1.0V
ADP3186
VCC
28
CSCOMP
18
100nF
CSSUM
17
CSREF
16
GND
19
VOS =
CSCOMP – 1V
40
Figure 3. Current Sense Amplifier, VOS
ADP3186
12V
10kΩ
200kΩ
80mV
1.0V
ADP3186
VCC
28
FB
8
COMP
9
200kΩ CSCOMP
18
CSSUM
17
CSREF
16
GND
19
Figure 4. Positioning Voltage
Rev. A | Page 5 of 24
5 Page 
CH1 = CSREF
CH2 = DELAY
CH3 = COMP
CH4 = PGD
Figure 8. Typical Start-Up Waveforms—Channel 1: PWRGD,
Channel 2: CSREF, Channel 3: DELAY, Channel 4: COMP
CURRENT LIMIT, SHORT-CIRCUIT, AND LATCH-
OFF PROTECTION
The ADP3186 compares a programmable current-limit setpoint
to the voltage from the output of the current sense amplifier.
The level of current limit is set with the resistor from the ILIMIT
pin to ground. During normal operation, the voltage on ILIMIT
is 3 V. The current through the external resistor is internally
scaled to give a current limit threshold of 10.4 mV/μA. If the
difference in voltage between CSREF and CSCOMP rises above
the current limit threshold, the internal current limit amplifier
controls the internal COMP voltage to maintain the average
output current at the limit.
After the limit is reached, the 3 V pull-up on the DELAY pin is
disconnected and the external delay capacitor is discharged
through the external resistor. A comparator monitors the DELAY
voltage and shuts off the controller when the voltage drops below
1.8 V. The current limit latch-off delay time is, therefore, set by the
RC time constant discharging from 3 V to 1.8 V. The Application
Information section discusses the selection of CDLY and RDLY.
Because the controller continues to cycle the phases during the
latch-off delay time, if the short is removed before the 1.8 V
threshold is reached, the controller returns to normal operation.
The recovery characteristic depends on the state of PWRGD. If
the output voltage is within the PWRGD window, the controller
resumes normal operation. However, if short circuit has caused
the output voltage to drop below the PWRGD threshold, a soft
start cycle is initiated.
The latch-off function can be reset by either removing and
reapplying VCC to the ADP3186, or by pulling the EN pin low
for a short time. To disable the short circuit latch-off function,
the external resistor to ground should be left open, and a high-
value (>1 MΩ) resistor should be connected from DELAY to
VCC. This prevents the DELAY capacitor from discharging, so
the 1.8 V threshold is never reached.
ADP3186
The resistor has an impact on the soft start time, because the
current through it adds to the internal 20 μA current source.
During startup when the output voltage is below 200 mV, a
secondary current limit is active. This is necessary, because the
voltage swing of CSCOMP cannot go below ground. This
secondary current limit controls the internal COMP voltage to
the PWM comparators to 2 V. This limits the voltage drop
across the low-side MOSFETs through the current balance
circuitry.
An inherent per phase current limit protects individual phases,
if one or more phases stops functioning because of a faulty
component. This limit is based on the maximum normal mode
COMP voltage.
Figure 9. Overcurrent Latch-Off Waveforms—Channel 1: CSREF,
Channel 2: DELAY, Channel 3: COMP, Channel 4: Phase 1 Switch Node
DYNAMIC VID
The ADP3186 has the ability to dynamically change the VID
input while the controller is running. This allows the output
voltage to change while the supply is running and supplying
current to the load. This is commonly referred to as VID
on-the-fly (OTF). A VID OTF can occur under either light or
heavy load conditions. The processor signals the controller by
changing the VID inputs in multiple steps from the start code to
the finish code. This change can be positive or negative.
When a VID input changes state, the ADP3186 detects the
change and ignores the DAC inputs for a minimum of 400 ns.
This time prevents a false code due to logic skew while the five
VID inputs are changing. Additionally, the first VID change
initiates the PWRGD and CROWBAR blanking functions for a
minimum of 100 μs to prevent a false PWRGD or CROWBAR
event. Each VID change resets the internal timer.
Rev. A | Page 11 of 24
11 Page | ||
| Páginas | Total 24 Páginas | |
| PDF Descargar | [ Datasheet ADP3186.PDF ] | |
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