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PDF AD5664 Data sheet ( Hoja de datos )
| Número de pieza | AD5664 | |
| Descripción | (AD5624 / AD5664) nanoDACs | |
| Fabricantes | Analog Devices | |
| Logotipo |  |
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2.7 V to 5.5 V, 450 μA, Rail-to-Rail Output,
Quad, 12-/16-Bit nanoDACs®
AD5624/AD5664
FEATURES
Low power, quad nanoDACs
AD5664: 16 bits
AD5624: 12 bits
Relative accuracy: ±12 LSBs max
Guaranteed monotonic by design
10-lead MSOP and 3 mm × 3 mm LFCSP_WD
2.7 V to 5.5 V power supply
Power-on reset to zero
Per channel power-down
Serial interface, up to 50 MHz
APPLICATIONS
Process control
Data acquisition systems
Portable battery-powered instruments
Digital gain and offset adjustment
Programmable voltage and current sources
Programmable attenuators
FUNCTIONAL BLOCK DIAGRAM
VDD
GND
VREF
AD5624/AD5664
SCLK
SYNC
DIN
INTERFACE
LOGIC
INPUT
REGISTER
DAC
REGISTER
STRING
DAC A
BUFFER
VOUTA
INPUT
REGISTER
DAC
REGISTER
STRING
DAC B
BUFFER
VOUTB
INPUT
REGISTER
DAC
REGISTER
STRING
DAC C
BUFFER
VOUTC
INPUT
REGISTER
DAC
REGISTER
POWER-ON
RESET
STRING
DAC D
BUFFER
POWER-DOWN
LOGIC
VOUTD
Figure 1.
Table 1. Related Devices
Part No.
AD5624R/AD5644R/AD5664R
Description
2.7 V to 5.5 V quad, 12-, 14-,
16-bit DACs with internal
reference
GENERAL DESCRIPTION
The AD5624/AD5664, members of the nanoDAC family, are
low power, quad, 12-, 16-bit buffered voltage-out DACs that
operate from a single 2.7 V to 5.5 V supply and are guaranteed
monotonic by design.
The AD5624/AD5664 require an external reference voltage to
set the output range of the DAC. The part incorporates a power-
on reset circuit that ensures the DAC output powers up to 0 V
and remains there until a valid write takes place. The parts
contain a power-down feature that reduces the current
consumption of the device to 480 nA at 5 V and provides
software-selectable output loads while in power-down mode.
The low power consumption of these parts in normal operation
makes them ideally suited to portable battery-operated
equipment. The power consumption is 2.25 mW at 5 V, going
down to 2.4 μW in power-down mode.
The AD5624/AD5664 on-chip precision output amplifier allows
rail-to-rail output swing to be achieved.
The AD5624/AD5664 use a versatile 3-wire serial interface that
operates at clock rates up to 50 MHz, and are compatible with
standard SPI®, QSPI™, MICROWIRE™, and DSP interface
standards.
PRODUCT HIGHLIGHTS
1. Relative accuracy: ±12 LSBs maximum.
2. Available in 10-lead MSOP and 10-lead, 3 mm × 3 mm,
LFCSP_WD.
3. Low power, typically consumes 1.32 mW at 3 V and
2.25 mW at 5 V.
4. Maximum settling time of 4.5 μs (AD5624) and 7 μs
(AD5664).
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
©2006 Analog Devices, Inc. All rights reserved.
1 page  
AD5624/AD5664
TIMING CHARACTERISTICS
All input signals are specified with tR = tF = 1 ns/V (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2 (see Figure 2).
VDD = 2.7 V to 5.5 V; all specifications TMIN to TMAX, unless otherwise noted.
Table 4.
Parameter1
t1 2
t2
t3
t4
t5
t6
t7
t8
t9
t10
Limit at TMIN, TMAX
VDD = 2.7 V to 5.5 V
20
9
9
13
5
5
0
15
13
0
Unit
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
Conditions/Comments
SCLK cycle time
SCLK high time
SCLK low time
SYNC to SCLK falling edge setup time
Data setup time
Data hold time
SCLK falling edge to SYNC rising edge
Minimum SYNC high time
SYNC rising edge to SCLK fall ignore
SCLK falling edge to SYNC fall ignore
1 Guaranteed by design and characterization, not production tested.
2 Maximum SCLK frequency is 50 MHz at VDD = 2.7 V to 5.5 V.
TIMING DIAGRAM
SCLK
SYNC
DIN
t10
t8
t4
DB23
t6
t5
t1
t3 t2
t9
t7
DB0
Figure 2. Serial Write Operation
Rev. 0 | Page 5 of 24
5 Page 
2.538
2.537
2.536
2.535
2.534
2.533
2.532
2.531
2.530
2.529
2.528
2.527
2.526
2.525
2.524
2.523
2.522
2.521
0
VDD = VREF = 5V
TA = 25°C
5ns/SAMPLE NUMBER
GLITCH IMPULSE = 9.494nV
1LSB CHANGE AROUND
MIDSCALE (0x8000 TO 0x7FFF)
50 100 150 200 250 300 350 400 450
SAMPLE NUMBER
512
Figure 22. Digital-to-Analog Glitch Impulse (Negative)
2.498
2.497
2.496
VDD = VREF = 5V
TA = 25°C
5ns/SAMPLE NUMBER
ANALOG CROSSTALK = 0.424nV
2.495
2.494
2.493
2.492
2.491
0
50 100 150 200 250 300 350 400 450
SAMPLE NUMBER
Figure 23. Analog Crosstalk
–20
VDD = 5V
–30
TA = 25°C
DAC LOADED WITH FULL SCALE
–40 VREF = 2V ± 0.3V p-p
512
–50
–60
–70
–80
–90
–100
2k 4k 6k 8k
(Hz)
Figure 24. Total Harmonic Distortion
10k
AD5624/AD5664
16
VREF = VDD
TA = 25°C
14
12
VDD = 3V
10
8 VDD = 5V
6
4
0 1 2 3 4 5 6 7 8 9 10
CAPACITANCE (nF)
Figure 25. Settling Time vs. Capacitive Load
VDD = VREF = 5V
TA = 25°C
DAC LOADED WITH MIDSCALE
1
Y AXIS = 2µV/DIV
X AXIS = 4s/DIV
Figure 26. 0.1 Hz to 10 Hz Output Noise Plot
800
VDD = VREF = 5V
700 TA = 25°C
600
500
400
300
200
100
0
10
100 1k 10k 100k
FREQUENCY (Hz)
Figure 27. Noise Spectral Density
1M
Rev. 0 | Page 11 of 24
11 Page | ||
| Páginas | Total 24 Páginas | |
| PDF Descargar | [ Datasheet AD5664.PDF ] | |
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