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PDF AD5522 Data sheet ( Hoja de datos )
| Número de pieza | AD5522 | |
| Descripción | Quad Parametric Measurement Unit | |
| Fabricantes | Analog Devices | |
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Preliminary Technical Data
Quad Parametric Measurement Unit With
Integrated 16-Bit Level Setting DACs
AD5522
FEATURES
Quad Parametric Measurement Unit
FV, FI, FN, MV, MI Functions
4 Programmable Current Ranges (Internal RSENSE)
5uA, 20uA, 200uA and 2mA
1 Programmable Current Range up to 64mA (external RSENSE)
22.5 V FV Range with Asymmetrical Operation
Integrated 16-Bit DACs Provide Programmable Levels
Offset and Gain Correction on Chip
Low Capacitance Outputs Suited to Relay Less Systems
On-chip Comparators Per Channel
FI Voltage Clamps & FV Current Clamps
Guard Drive Amplifier
System PMU connections
Programmable Temperature Shutdown Feature
SPI/Microwire/DSP & LVDS Compatible Interfaces
Compact 80 lead TQFP Package with Exposed Pad (Top Or
Bottom)
APPLICATIONS
Automatic Test Equipment (ATE)
per pin Parametric Measurement Unit
Continuity & Leakage Testing
Device Power Supply
Instrumentation
SMU (Source Measure Unit)
Precision Measurement
AGND AVSS(0-4) AVDD(0-4) DVCC
DGND
PRODUCT OVERVIEW
The AD5522 is a high performance, highly integrated parametric
measurement unit consisting of four independent channels. Each
PPMU channel includes five, 16-bit, voltage out DACs setting the
programmable inputs levels for the force voltage input, clamp and
comparator inputs (high and low). Five programmable force and
measure current ranges are available ranging from 5µA to 64mA.
Four of these ranges use on chip sense resistors, while a high
current range up to 64mA is available per channel using off chip
sense resistors. Currents in excess of 64mA require an external
amplifier. Low capacitance DUT connections (FOH, EXT FOH)
ensure the device is suited to relay less test systems.
The PMU functions are controlled via a simple three wire serial
interface compatible with SPI/QSPI/Microwire and DSP interface
standards. Interface clocks of 50MHz allow fast updating of modes.
LVDS (Low Voltage Differential Signaling) interface protocol at
100MHz is also supported. Comparator outputs are provided per
channel for device go no-go testing and characterization. Control
registers provide easy way of changing force or measure conditions,
DAC levels and selected current ranges. SDO (serial data out)
allows the user to readback information for diagnostic purposes.
CCOMP (0-3)
SYS_FORCE SYS_SENSE
VREF
REFGND
MEASOUT (0-3)
AGND (0-3)
16
X1 REG
16 M REG
16 C REG *2
X2 REG
*2
16-Bit
16 CLH DAC
OFFSET DAC
x4
CLH
EN
SW 3
16
16
16 X1 REG
M REG
C REG
*6
16
16 X1 REG
M REG
16 C REG *2
*6
16-Bit
16 FIN DAC
X2 REG
X2 REG
*2
16 16-Bit
CLL DAC
FIN SW 1
AGNDx
+
FORCE
AMPLIFER
-
SW 2
SW 10
OFFSET DAC
BIAS TO
CENTER
IRANGE
CLL
+
-
INTERNAL RANGE SELECT
(5uA, 20uA, 200uA, 2mA) 60Ω 1kΩ
RSENSE
SW 4
SW 6
SW 5
SW 7
SW 8
10kΩ
+
SW 12
MEASOUT
MUX & GAIN
x1/x0.2
TEMP
SENSOR
16
*6
16
16 X1 REG
M REG
C REG
*6
16-Bit
X2 REG 16 CPH DAC
SW 11
x5 or x10
-
AGNDx +
MEASURE
CURRENT
IN AMP
+
-
+
-
16
16 *6
16 X1 REG
M REG
C REG
*6 16-Bit CPL
16 CPL DAC
X2 REG
-
+
COM PARATO R
CPH
-+
x1
-
MEASURE
VOLTAGE
IN AMP
+ DUTGND
-
SW 9
SW 13
SW 14
SW 16
GUARD AMP
SW 15
10kΩ
AGNDx
16-Bit
16 OFFSET
DAC
16
POWER ON
RESET
TO ALL DAC
OUTPUT
AMPLIFIERS
SERIAL
INTERFACE
TO
MEASOUT
MUX
TEMP
SENSOR
CLAMP &
GUARD
ALARM
EXTFOH(0-3)
CFF(0-3)
FOH(0-3)
EXTMEASIH(0-3)
EXTMEASIL(0-3)
EXTERNAL
RSENSE
(CURRENTS
UP TO 64mA)
MEASVH (0-3)
GUARD (0-3)
GUARDIN (0-3)/
DUTGND (0-3)
DUTGND
DUT
TMPALM
CGALM
RESET
SDO SCLK SDI SYNC BUSY LOAD LVDS/ CPOL0/ CPOH0/
SPI SCLK SDI
CPOL1/ CPOH1/ CPOL2 CPOH2 CPOL3 CPOH3
SYNC SDO
/CPO0 /CPO1 /CPO2 /CPO3
Figure 1. Functional Block Diagram
Rev.PrL
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
©2006 Analog Devices, Inc. All rights reserved.
1 page  
Preliminary Technical Data
AD5522
Parameter
COMPARATOR
Comparator Span
Offset Error
Propagation delay2
VOLTAGE CLAMPS
Clamp Span
Positive Clamp Accuracy
Negative Clamp Accuracy
Recovery Time2
Activation Time2
CURRENT CLAMPS
Clamp Accuracy
Recovery Time2
Activation Time2
FOH, EXTFOH, EXTMEASIL,
EXTMEASIH, CFF
Pin Capacitance2
Leakage Current
Leakage Current Tempco2
MEASVH
Pin Capacitance2
Leakage/Bias Current
Leakage Current Tempco2
SYS_SENSE
Pin Capacitance2
SYS_SENSE Impedance
Leakage Current
Leakage Current Tempco2
SYS_FORCE
Pin Capacitance2
SYS_FORCE Impedance
Leakage Current
Leakage Current Tempco2
COMBINED LEAKAGE at DUT
Leakage Current
Leakage Current Tempco2
DUTGND
Voltage Range
Leakage Current
MEASURE OUTPUT (MEASOUT)
Measure Output Voltage Span
Measure Pin output Impedance
Output leakage current
Output Capacitance2
Short Circuit Current2
MEASOUT enable time
MEASOUT disable time
MEASOUT MI to MV switching time
GUARD OUTPUT
Guard Output Voltage Span
Guard Output Offset
Short Circuit Current2
Load Capacitance2
Guard Output Impedance
Slew Rate2
Min
-10
-150
Prog’d
Clamp
value
Typ1
Max
Units
Test Conditions/Comments
22.5 V
10 mV
1 TBD μs
22.5 V
150 mV
mV
TBD TBD μs
TBD TBD μs
Programmed
Clamp value
+15
% of FSC
range
Clamp current scales with selected range
TBD TBD μs
TBD TBD μs
3
-3
±0.1
3
-3
±0.1
3
1
-3
±0.1
3
60
-3
±0.1
-15
±0.5
-500
-1
-3
-10
TBD
TBD
TBD
-10
-10
100
3
TBD pF
3 nA
On or off switch leakage
nA/ oC
TBD pF
3 nA
nA/ oC
SYS_Sense Connected, Force Amplifier Inhibited
TBD pF
1.3 kΩ
3 nA
nA/ oC
SYS_Force Connected, Force Amplifier Inhibited
TBD pF
80 Ω
3 nA
nA/ oC
Includes FOH, MEASVH, SYS_SENSE, SYS_FORCE,
EXTMEASIL
15 nA
nA/oC typ
500 mV
1 μA
22.5 V
100 Ω
3 nA
15 pF
10 mA
TBD ns
TBD ns
TBD ns
With respect to AGND
Software Programmable output range
With SW12 off
Closing SW12
Opening SW12
22.5 V
10 mV
10 mA
50 nF
Ω
V/μs
CLOAD = TBD pf
Rev. PrL | Page 5 of 45
5 Page 
Preliminary Technical Data
ABSOLUTE MAXIMUM RATINGS
Table 3. AD5522 Absolute Maximum Ratings
Parameter
Rating
Supply Voltage AVDD to AVSS
AVDD to AGND
AVSS to AGND
VREF to AGND
DUTGND, REFGND, AGND
DVCC to DGND
Digital Inputs to DGND
Analog Inputs to AGND
Storage Temperature
34V
-0.3V to 34V
0.3V to -34V
-0.3 V, +7V
AVDD +0.3V to AVSS -0.3V
- 0.3V to 7V
- 0.3V to DVCC +0.3V
AVSS - 0.3V to AVDD +0.3V
–65°C to +125°C
Operating Junction Temperature +25 to +90°C
Reflow Soldering
Peak Temperature
230°C
Time at Peak Temperature
10s to 40s
Junction Temperature
150°C max
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or
any other condition s above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
AD5522
THERMAL RESISTANCE3
Thermal resistance values are specified for the worst-case
conditions, i.e., specified for device soldered in circuit board for
surface mount packages.
Table 4. Thermal Resistance (JEDEC 4 layer (1S2P) board)
Air Flow (LFPM)
0 200 500 Unit
TQFP Exposed Pad Down θJA 22.3 17.2 15.1 °C/W
θJC 0.3
°C/W
TQFP Exposed Pad Up
θJA TBD TBD TBD °C/W
θJC 4.8
°C/W
Table 5. Thermal Resistance (JEDEC 4 layer (1S2P) board
with cooling plate4 at 45°C, natural convection at 55°C
ambient)
Package Thermals
θJA θJA Unit
TQFP Exposed Pad Down
5.4 4.8 °C/W
TQFP Exposed Pad Up
3.0 0.3 °C/W
3 Simulated Thermal information.
4 Assumes perfect thermal contact between cooling plate and exposed
paddle
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the
human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
Rev. PrL | Page 11 of 45
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet AD5522.PDF ] | |
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