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PDF AD5384 Data sheet ( Hoja de datos )
| Número de pieza | AD5384 | |
| Descripción | 14-Bit Voltage Output DAC | |
| Fabricantes | Analog Devices | |
| Logotipo |  |
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1. AD5384  Hay una vista previa y un enlace de descarga de AD5384 (archivo pdf) en la parte inferior de esta página. Total 30 Páginas | ||
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40-Channel, 3 V/5 V, Single-Supply,
Serial, 14-Bit Voltage Output DAC
AD5384
FEATURES
Guaranteed monotonic
INL error: ±4 LSB max
On-chip 1.25 V/2.5 V, 10 ppm/°C reference
Temperature range: –40°C to +85°C
Rail-to-rail output amplifier
Power-down
Package type: 100-lead CSPBGA (10 mm × 10 mm)
User Interfaces:
Serial (SPI-®/QSPI-™/MICROWIRE-™/DSP-compatible,
featuring data readback)
I2C-®compatible
INTEGRATED FUNCTIONS
Channel monitor
Simultaneous output update via LDAC
Clear function to user-programmable code
Amplifier boost mode to optimize slew rate
User-programmable offset and gain adjust
Toggle mode enables square wave generation
Thermal monitor
APPLICATIONS
Variable optical attenuators (VOA)
Level setting (ATE)
Optical micro-electro-mechanical systems (MEMS)
Control systems
Instrumentation
PD
SYNC/AD 0
DCEN/AD 1
DVDD (×3)
DGND (×4)
FUNCTIONAL BLOCK DIAGRAM
AVDD (×5)
AGND (×5) DAC GND (×5)
REFGND
REFOUT/REFIN SIGNAL GND (×5)
AD5384
1.25V/2.5V
REFERENCE
SDO
DIN/SDA
SCLK/SCL
SPI/I2C
INTERFACE
CONTROL
LOGIC
STATE
MACHINE
+
CONTROL
LOGIC
RESET
BUSY
CLR
POWER-ON
RESET
VOUT0……VOUT38
39-TO-1
MUX
14 INPUT 14
REG 0
14 m REG 0
14 c REG 0
14 INPUT 14
REG 1
14 m REG 1
14 c REG 1
14 INPUT 14
REG 6
14 m REG 6
14 c REG 6
14 INPUT 14
REG 7
14 m REG 7
14 c REG 7
14
DAC 14
REG 0
DAC 0
14
DAC 14
REG 1
DAC 1
14
DAC 14
REG 6
DAC 6
14
DAC 14
REG 7
DAC 7
×5
R
R
R
R
R
R
R
R
VOUT0
VOUT1
VOUT2
VOUT3
VOUT4
VOUT5
VOUT6
VOUT7
VOUT8
VOUT38
VOUT39/MON_OUT
LDAC
Figure 1.
Rev. A
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.326.8703 © 2004 Analog Devices, Inc. All rights reserved.
1 page  
AD5384
Parameter
LOGIC OUTPUTS (BUSY, SDO)3
VOL, Output Low Voltage
VOH, Output High Voltage
VOL, Output Low Voltage
VOH, Output High Voltage
High Impedance Leakage Current
High Impedance Output Capacitance
LOGIC OUTPUT (SDA)3
VOL, Output Low Voltage
Three-State Leakage Current
Three-State Output Capacitance
POWER REQUIREMENTS
AVDD
DVDD
Power Supply Sensitivity3
∆Midscale/∆ΑVDD
AIDD
DIDD
AIDD (Power-Down)
DIDD (Power-Down)
Power Dissipation
AD5384-51 Unit
Test Conditions/Comments
0.4
DVDD – 1
0.4
DVDD – 0.5
±1
5
V max
V min
V max
V min
µA max
pF typ
DVDD = 5 V ± 10%, sinking 200 µA
DVDD = 5 V ± 10%, sourcing 200 µA
DVDD = 2.7 V to 3.6 V, sinking 200 µA
DVDD = 2.7 V to 3.6 V, sourcing 200 µA
SDO only
SDO only
0.4 V max
0.6 V max
±1 µA max
8 pF typ
ISINK = 3 mA
ISINK = 6 mA
4.5/5.5
2.7/5.5
V min/max
V min/max
–85
0.375
0.475
1
2
20
80
dB typ
mA/channel max
mA/channel max
mA max
µA max
µA max
mW max
Outputs unloaded, boost off; 0.25 mA/channel typ
Outputs unloaded, boost on; 0.32 5mA/channel typ
VIH = DVDD, VIL = DGND
Typically 200 nA
Typically 3 µA
Outputs unloaded, boost off, AVDD = DVDD = 5 V
1 AD5384-5 is calibrated using an external 2.5 V reference. Temperature range for all versions: –40°C to +85°C.
2 Accuracy guaranteed from VOUT = 10 mV to AVDD – 50 mV.
3 Guaranteed by characterization, not production tested.
4 Default on the AD5384-5 is 2.5 V. Programmable to 1.25 V via CR12 in the AD5384 control register; operating the AD5384-5 with a 1.25 V reference will lead to
degraded accuracy specifications.
Rev. A | Page 5 of 36
5 Page 
SCLK
SYNC
DIN
BUSY
LDAC1
VOUT1
1
t4
t7
2
t3
t6
t8 t9
DB23
t1
24
t2 t5
DB0
t10
t11
t12 t13
t15
LDAC2
VOUT2
CLR
t18
VOUT 1LDAC ACTIVE DURING BUSY
2LDAC ACTIVE AFTER BUSY
t19
24
t17
t14
t13
t16 t17
Figure 3. Serial Interface Timing Diagram (Standalone Mode)
SCLK
SYNC
DIN
SDO
SCLK
SYNC
DIN
SDO
LDAC
24
t7A
48
DB23
DB0
DB23
DB0
INPUT WORD SPECIFIES
REGISTER TO BE READ
DB23
NOP CONDITION
DB0
UNDEFINED
SELECTED REGISTER
DATA CLOCKED OUT
Figure 4. Serial Interface Timing Diagram (Data Readback Mode)
t1
t7
t4
t8 t9
DB23
t3
24
t2
DB0 DB23
48
t21
t22
DB0
INPUT WORD FOR DAC N
UNDEFINED
t20
DB23
INPUT WORD FOR DAC N + 1
INPUT WORD FOR DAC N
DB0
t13
t23
Figure 5. Serial Interface Timing Diagram (Daisy-Chain Mode)
Rev. A | Page 11 of 36
AD5384
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet AD5384.PDF ] | |
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