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What is AD5362?

This electronic component, produced by the manufacturer "Analog Devices", performs the same function as "(AD5362 / AD5363) Voltage-Output DAC".


AD5362 Datasheet PDF - Analog Devices

Part Number AD5362
Description (AD5362 / AD5363) Voltage-Output DAC
Manufacturers Analog Devices 
Logo Analog Devices Logo 


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Preliminary Technical Data
8-Channel, 16/14-Bit,
Serial Input, Voltage-Output DAC
AD5362/AD5363
FEATURES
8-channel DAC in 52-LQFP and 56-LFCSP
Guaranteed monotonic to 16/14 bits
Nominal output voltage range of -10 V to +10 V
Multiple output spans available
Temperature Monitoring Function
Channel Monitoring Multiplexer
GPIO Function
System calibration function allowing user-programmable
offset and gain
Channel grouping and addressing features
Data error checking feature
SPI compatible serial interface
2.5 V to 5.5 V JEDEC-compliant digital levels
Power-on reset
Digital reset (RESET)
Clear function to user-defined SIGGND (CLR pin)
Simultaneous update of DAC outputs (LDAC pin)
APPLICATIONS
Instrumentation
Industrial Control System
PLC Analog I/O Cards
Level setting in automatic test equipment (ATE)
Variable optical attenuators (VOA)
Precision Medical Instruments
TEMP_OUT
PEC
MON_IN0
MON_IN1
MON_OUT
GPIO
BIN/2SCOMP
SYNC
SDI
SCLK
SDO
BUSY
RESET
CLR
FUNCTIONAL BLOCK DIAGRAM
DVCC VDD VSS AGND DNGD
LDAC
TEMP
SENSOR
CONTROL
REGISTER
8
VOUT0 -
VOUT7
MUX
6
GPIO
REGISTER
2
SERIAL
INTERFACE
AD5362, n = 16
AD5363, n = 14
4 A/B SELECT 4
REGISTER
TO
MUX 2's
n
n
X1 REGISTER
n A/B
MUX
nn
M REGISTER
n C REGISTER
n
······ ······ ······ ······
n
n
X1 REGISTER
nn
M REGISTER
n
C REGISTER
n A/B
MUX
n
STATE
MACHINE
n
POWER-ON
RESET
AD5362/
AD5363
4 A/B SELECT 4
TO
REGISTER
MUX 2's
n
n
X1 REGISTER
n A/B
MUX
nn
M REGISTER
n
n
C REGISTER
······ ······ ······ ······
n
n
X1 REGISTER
nn
M REGISTER
n
C REGISTER
n A/B
MUX
n
14 OFS0 14 OFFSET
REGISTER
DAC 0
X2A REGISTER
X2B REGISTER
·
·
·
·
·
·
X2A REGISTER
X2B REGISTER
MUX n
2
·
·
·
·
·
·
MUX n
2
DAC 0 n
REGISTER
·
·
·
·
·
·
DAC 3 n
REGISTER
DAC 0
·
···
··
DAC 3
14 OFS1 14 OFFSET
REGISTER
DAC 1
X2A REGISTER
X2B REGISTER
·
·
·
·
·
·
X2A REGISTER
X2B REGISTER
MUX n
2
·
·
·
·
·
·
MUX n
2
DAC 0 n
REGISTER
·
·
·
·
·
·
DAC 3 n
REGISTER
DAC 0
·
···
··
DAC 3
BUFFER
GROUP 0
BUFFER
OUTPUT BUFFER
AND POWER
DOWN CONTROL
·
···
··
OUTPUT BUFFER
AND POWER
DOWN CONTROL
GROUP 1
BUFFER
OUTPUT BUFFER
AND POWER
DOWN CONTROL
··
··
··
OUTPUT BUFFER
AND POWER
DOWN CONTROL
5362-0001B
VREF0
VOUT0
VOUT1
VOUT2
VOUT3
SIGGND0
VREF1
VOUT4
VOUT5
VOUT6
VOUT7
SIGGND1
Figure 1.
AD5362/AD5363—Protected by U.S. Patent No. 5,969,657; other patents pending
Rev. PrF
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective companies.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.326.8703 © 2006 Analog Devices, Inc. All rights reserved.

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AD5362 equivalent
Preliminary Technical Data
Parameter
POWER REQUIREMENTS
DVCC
VDD
VSS
Power Supply Sensitivity2
∆ Full Scale/∆ VDD
∆ Full Scale/∆ VSS
∆ Full Scale/∆ VCC
DICC
IDD
ISS
Power Dissipation
Power Dissipation Unloaded (P)
Junction Temperature3
B Version 1 Unit
Test Conditions/Comments2
2.3/5.5
8/16.5
−4.5/−16.5
V min/max
V min/max
V min/max
−75 dB typ
−75 dB typ
−90 dB typ
2
mA max
VCC = 5.5 V, VIH = VCC, VIL = GND.
5
mA max
Outputs unloaded.
5
mA max
Outputs unloaded.
350 mW
130
°C max
TJ = TA + PTOTAL × θJ.
1 Temperature range for B Version: −40°C to +85°C. Typical specifications are at 25°C.
2 Guaranteed by design and characterization, not production tested.
3 Where θJ represents the package thermal impedance.
AD5362/AD5363
AC CHARACTERISTICS
DVCC = 2.5 V; VDD = 15 V; VSS = −15 V; VREF = 3 V; AGND = DGND = SIGGND = 0 V; CL = 200pF; RL = 10 kΩ;
Gain (m), Offset(c) and DAC Offset registers at default value; all specifications TMIN to TMAX, unless otherwise noted.
Table 3. AC Characteristics
Parameter
B Version
DYNAMIC PERFORMANCE1
Output Voltage Settling Time
20
30
Slew Rate
1
Digital-to-Analog Glitch Energy
20
Glitch Impulse Peak Amplitude
10
Channel-to-Channel Isolation
100
DAC-to-DAC Crosstalk
40
10
Digital Crosstalk
0.1
Digital Feedthrough
1
Output Noise Spectral Density @ 10 kHz 250
1Guaranteed by design and characterization. Not production tested
Unit Test Conditions/Comments
µs typ
µs max
V/µs typ
nV-s typ
mV max
dB typ
nV-s typ
nV-s typ
nV-s typ
nV-s typ
nV/(Hz)1/2 typ
Full-scale change
DAC latch contents alternately loaded with all 0s and all 1s.
VREF = 2 V p-p, 1 kHz.
Between DACs in the same group.
Between DACs from different groups.
Effect of input bus activity on DAC output under test.
VREF = 0 V.
Rev. PrF | Page 5 of 25


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