PDF ADF4360-8 Data sheet ( Hoja de datos )

Número de pieza	ADF4360-8
Descripción	Integrated Synthesizer and VCO
Fabricantes	Analog Devices
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No Preview Available ! Data Sheet Integrated Synthesizer and VCO ADF4360-8 FEATURES Output frequency range: 65 MHz to 400 MHz 3.0 V to 3.6 V power supply 1.8 V logic compatibility Integer-N synthesizer Programmable output power level 3-wire serial interface Digital lock detect Hardware and software power-down mode APPLICATIONS System clock generation Test equipment Wireless LANs CATV equipment GENERAL DESCRIPTION The ADF4360-8 is an integrated integer-N synthesizer and voltage-controlled oscillator (VCO). The ADF4360-8 center frequency is set by external inductors. This allows a frequency range of between 65 MHz to 400 MHz. Control of all the on-chip registers is through a simple 3-wire interface. The device operates with a power supply ranging from 3.0 V to 3.6 V and can be powered down when not in use. FUNCTIONAL BLOCK DIAGRAM AVDD DVDD RSET CE ADF4360-8 REFIN 14-BIT R COUNTER CLK DATA LE 24-BIT DATA REGISTER 24-BIT FUNCTION LATCH LOCK DETECT MULTIPLEXER MUTE CHARGE PUMP PHASE COMPARATOR MUXOUT CP VVCO VTUNE L1 L2 CC CN 13-BIT B COUNTER N=B VCO CORE OUTPUT STAGE RFOUTA RFOUTB AGND DGND CPGND Figure 1. Rev. D Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no re- sponsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 ©2004-2016 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com 1 page ADF4360-8 Data Sheet Parameter Frequency Pulling (Open Loop) Harmonic Content (Second) Harmonic Content (Third) Output Power5, 7 Output Power5, 8 Output Power Variation VCO Tuning Range NOISE CHARACTERISTICS5 VCO Phase Noise Performance9 Synthesizer Phase Noise Floor10 Phase Noise Figure of Merit10 In-Band Phase Noise11, 12 RMS Integrated Phase Error13 Spurious Signals due to PFD Frequency12, 14 Level of Unlocked Signal with MTLD Enabled B Version 10 −16 −21 −9/0 −14/−9 ±3 1.25/2.5 −120 −139 −140 −142 −160 −150 −142 −215 −102 0.09 −75 −70 Unit Hz typ dBc typ dBc typ dBm typ dBm typ dB typ V min/max dBc/Hz typ dBc/Hz typ dBc/Hz typ dBc/Hz typ dBc/Hz typ dBc/Hz typ dBc/Hz typ dBc/Hz typ dBc/Hz typ Degrees typ dBc typ dBm typ Test Conditions/Comments Into 2.00 VSWR load. Using tuned load, programmable in 3 dB steps; see Table 7. Using 50 Ω resistors to VVCO, programmable in 3 dB steps; see Table 7. At 100 kHz offset from carrier. At 800 kHz offset from carrier. At 3 MHz offset from carrier. At 10 MHz offset from carrier. At 200 kHz PFD frequency. At 1 MHz PFD frequency. At 8 MHz PFD frequency. At 1 kHz offset from carrier. 100 Hz to 100 kHz. 1 Operating temperature range is –40°C to +85°C. 2 Guaranteed by design. Sample tested to ensure compliance. 3 ICP is internally modified to maintain constant loop gain over the frequency range. 4 TA = 25°C; AVDD = DVDD = VVCO = 3.3 V. 5 Unless otherwise stated, these characteristics are guaranteed for VCO core power = 5 mA. L1, L2 = 270 nH, 470 Ω resistors to GND in parallel with L1, L2. 6 Jumping from 88 MHz to 108 MHz. PFD frequency = 200 kHz; loop bandwidth = 10 kHz. 7 For more detail on using tuned loads, see the Output Matching section. 8 Using 50 Ω resistors to VVCO, into a 50 Ω load. 9 The noise of the VCO is measured in open-loop conditions. 10 The synthesizer phase noise floor is estimated by measuring the in-band phase noise at the output of the VCO and subtracting 20 log N (where N is the N divider value). The phase noise figure of merit subtracts 10 log (PFD frequency). 11 The phase noise is measured with the EV-ADF4360-8EB1Z evaluation board and the HP 8562E spectrum analyzer. The spectrum analyzer provides the REFIN for the synthesizer; offset frequency = 1 kHz. 12 fREFIN = 10 MHz; fPFD = 200 kHz; N = 1000; loop bandwidth = 10 kHz. 13 fREFIN = 10 MHz; fPFD = 1 MHz; N = 120; loop bandwidth = 100 kHz. 14 The spurious signals are measured with the EV-ADF4360-8EB1Z evaluation board and the HP 8562E spectrum analyzer. The spectrum analyzer provides the REFIN for the synthesizer; fREFOUT = 10 MHz at 0 dBm. Rev. D \| Page 4 of 24 5 Page ADF4360-8 CIRCUIT DESCRIPTION REFERENCE INPUT SECTION The reference input stage is shown in Figure 16. SW1 and SW2 are normally closed switches. SW3 is normally open. When power-down is initiated, SW3 is closed, and SW1 and SW2 are opened. This ensures that there is no loading of the REFIN pin on power-down. POWER-DOWN CONTROL NC 100k REFIN NC SW2 SW1 SW3 NO TO R COUNTER BUFFER Figure 16. Reference Input Stage N COUNTER The CMOS N counter allows a wide division ratio in the PLL feedback counter. The counters are specified to work when the VCO output is 400 MHz or less. To avoid confusion, this is re- ferred to as the B counter. It makes it possible to generate output frequencies that are spaced only by the reference frequency divided by R. The VCO frequency equation is fVCO  B  fREFIN / R where: fVCO is the output frequency of the VCO. B is the preset divide ratio of the binary 13-bit counter (3 to 8191). fREFIN is the external reference frequency oscillator. R COUNTER The 14-bit R counter allows the input reference frequency to be divided down to produce the reference clock to the phase fre- quency detector (PFD). Division ratios from 1 to 16,383 are allowed. PFD AND CHARGE PUMP The PFD takes inputs from the R counter and N counter (N = BP + A) and produces an output proportional to the phase and frequency difference between them. Figure 17 is a simpli- fied schematic. The PFD includes a programmable delay ele- ment that controls the width of the antibacklash pulse. This pulse ensures that there is no dead zone in the PFD transfer function, and minimizes phase noise and reference spurs. Two bits in the R counter latch, ABP2 and ABP1, control the width of the pulse (see Table 9). Data Sheet HI R DIVIDER UP D1 Q1 U1 CLR1 PROGRAMMABLE DELAY U3 ABP1 ABP2 HI N DIVIDER CLR2 DOWN D2 Q2 U2 VP CHARGE PUMP CP CPGND R DIVIDER N DIVIDER CP OUTPUT Figure 17. PFD Simplified Schematic and Timing (In Lock) MUXOUT AND LOCK DETECT The output multiplexer on the ADF4360-8 allows the user to access various internal points on the chip. The state of MUX- OUT is controlled by M3, M2, and M1 in the function latch. The full truth table is shown in Table 7. Figure 18 shows the MUXOUT section in block diagram form. DVDD DIGITAL LOCK DETECT R COUNTER OUTPUT N COUNTER OUTPUT MUX CONTROL MUXOUT Figure 18. MUXOUT Circuit DGND Rev. D \| Page 10 of 24 11 Page

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