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PDF ADG701L Data sheet ( Hoja de datos )
| Número de pieza | ADG701L | |
| Descripción | (ADG701L / ADG702L) CMOS Low Voltage 2 OHM SPST Switches | |
| Fabricantes | Analog Devices | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de ADG701L (archivo pdf) en la parte inferior de esta página. Total 12 Páginas | ||
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FEATURES
1.8 V to 5.5 V single supply
2 Ω (typical) on resistance
Low on resistance flatness
Guaranteed leakage specifications up to 85°C
–3 dB bandwidth > 200 MHz
Rail-to-rail operation
Fast switching times
tON 18 ns
tOFF 12 ns
Typical power consumption < 0.01 μW
TTL/CMOS-compatible
APPLICATIONS
Battery-powered systems
Communication systems
Sample-and-hold systems
Audio signal routing
Video switching
Mechanical reed relay replacement
GENERAL DESCRIPTION
The ADG701L/ADG702L are monolithic CMOS SPST switches.
These switches are designed using an advanced submicron
process that provides low power dissipation, yet offers high
switching speed, low on resistance, and low leakage currents.
In addition, −3 dB bandwidths of greater than 200 MHz can
be achieved.
The ADG701L/ADG702L can operate from a single 1.8 V to
5.5 V supply, making it ideal for use in battery-powered
instruments and with the new generation of DACs and ADCs
from Analog Devices.
Figure 1 and Figure 2 show that with a logic input of 1, the
switch of the ADG701L is closed, while that of the ADG702L
is open. Each switch conducts equally well in both directions
when on.
The ADG701L/ADG702L are packaged as 5-lead SOT-23,
6-lead SOT-23, and 8-lead MSOP.
CMOS Low Voltage
2 Ω SPST Switches
ADG701L/ADG702L
FUNCTIONAL BLOCK DIAGRAMS
ADG701L
SD
IN
SWITCHES SHOWN
FOR A LOGIC 1 INPUT
Figure 1.
ADG702L
SD
IN
SWITCHES SHOWN
FOR A LOGIC 1 INPUT
Figure 2.
PRODUCT HIGHLIGHTS
1. 1.8 V to 5.5 V single-supply operation. The ADG701L/
ADG702L offer high performance, including low on
resistance and fast switching times. The ADG701L/
ADG702L are fully specified and guaranteed with 3 V
and 5 V supply rails.
2. Very low RON (3 Ω maximum at 5 V, 5 Ω maximum at 3 V).
At 1.8 V operation, RON is typically 40 Ω over the
temperature range.
3. On resistance flatness RFLAT(ON) (1 Ω maximum).
4. −3 dB bandwidth > 200 MHz.
5. Low power dissipation. CMOS construction ensures low
power dissipation.
6. Fast tON/tOFF.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
©2006 Analog Devices, Inc. All rights reserved.
1 page  
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted.
Table 3.
Parameter
VDD to GND
Analog, Digital Inputs1
Continuous Current, S or D
Peak Current, S or D
Operating Temperature Range
Industrial (B Version)
Storage Temperature Range
Junction Temperature
MSOP Package, Power Dissipation
θJA Thermal Impedance
θJC Thermal Impedance
SOT-23 Package, Power Dissipation
θJA Thermal Impedance
θJC Thermal Impedance
Lead Temperature, Soldering
Vapor Phase (60 sec)
Infrared (15 sec)
Lead-free Reflow Soldering
Peak Temperature
Time at Peak Temperature
ESD
Rating
−0.3 V to +7 V
−0.3 V to VDD + 0.3 V or 30 mA,
whichever occurs first
30 mA
100 mA, pulsed at 1 ms,
10% duty cycle maximum
−40°C to +85°C
−65°C to +150°C
150°C
315 mW
206°C/W
44°C/W
282 mW
229.6°C/W
91.99°C/W
215°C
220°C
260 (+0/−5)°C
10 sec to 40 sec
2 kV
1 Overvoltages at IN, S, or D are clamped by internal diodes. Current should be
limited to the maximum ratings given.
ADG701L/ADG702L
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degrada-
tion or loss of functionality.
Rev. 0 | Page 5 of 12
5 Page 
OUTLINE DIMENSIONS
3.00
BSC
3.00
BSC
8
1
5
4.90
BSC
4
PIN 1
0.65 BSC
0.15
0.00
0.38
0.22
COPLANARITY
0.10
1.10 MAX
SEATING
PLANE
0.23
0.08
8°
0°
0.80
0.60
0.40
COMPLIANT TO JEDEC STANDARDS MO-187-AA
Figure 21. 8-Lead Mini Small Outline Package [MSOP]
(RM-8)
Dimensions shown in millimeters
ADG701L/ADG702L
2.90 BSC
1.60 BSC
PIN 1
INDICATOR
1.30
1.15
0.90
0.15 MAX
65 4
12
3
2.80 BSC
1.90
BSC
0.95 BSC
1.45 MAX
0.22
0.08
0.50
0.30 SEATING
PLANE
10° 0.60
4° 0.45
0° 0.30
COMPLIANT TO JEDEC STANDARDS MO-178-AB
Figure 22. 6-Lead Small Outline Transistor Package [SOT-23]
(RT-6)
Dimensions shown in millimeters
2.90 BSC
1.60 BSC
54
12 3
2.80 BSC
PIN 1
1.30
1.15
0.90
1.90
BSC
0.95 BSC
0.15 MAX
1.45 MAX
0.22
0.08
0.50 SEATING
0.30 PLANE
10°
5°
0°
0.60
0.45
0.30
COMPLIANT TO JEDEC STANDARDS MO-178-AA
Figure 23. 5-Lead Small Outline Transistor Package [SOT-23]
(RJ-5)
Dimensions shown in millimeters
Rev. 0 | Page 11 of 12
11 Page | ||
| Páginas | Total 12 Páginas | |
| PDF Descargar | [ Datasheet ADG701L.PDF ] | |
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