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PDF ADG1308 Data sheet ( Hoja de datos )
| Número de pieza | ADG1308 | |
| Descripción | (ADG1308 / ADG1309) Multiplexers | |
| Fabricantes | Analog Devices | |
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FEATURES
33 V supply range
130 Ω on resistance
Fully specified at ±15 V/+12 V
3 V logic-compatible inputs
Rail-to-rail operation
Break-before-make switching action
16-lead TSSOP and 16-lead SOIC_N
Upgrade for the ADG508A/ADG509A
APPLICATIONS
Audio and video routing
Test equipment
Data acquisition systems
Battery-powered systems
Communication systems
Signal routing
4- and 8-Channel
±15 V/+12 V Multiplexers
ADG1308/ADG1309
FUNCTIONAL BLOCK DIAGRAMS
ADG1308
S1
ADG1309
S1A
S4A
DA
D
S1B
DB
S8 S4B
1-OF-8
DECODER
1-OF-4
DECODER
A0 A1 A2 EN
Figure 1.
A0 A1 EN
GENERAL DESCRIPTION
The ADG1308 and ADG1309 are monolithic analog multi-
plexers consisting of eight single channels and four differential
channels, respectively. The ADG1308 switches one of eight
inputs to a common output as determined by the 3-bit binary
address lines A0, A1, and A2. The ADG1309 switches one of
four differential inputs to a common differential output as
determined by the 2-bit binary address lines A0 and A1. An EN
input on both devices is used to enable or disable the device.
When disabled, all channels are switched off.
When the switches are on, each switch conducts equally well
in both directions and has an input signal range that extends to
the power supplies. In the off condition, signal levels up to the
supplies are blocked. All switches exhibit break-before-make
switching action for use in multiplexer applications. Inherent in
the design is the low charge injection for minimum transients
when switching the digital inputs.
Fast switching speed coupled with high signal bandwidth makes
the parts suitable for video signal switching. CMOS
construction ensures ultra low power dissipation, making the
parts ideally suited for portable and battery-powered
instruments.
PRODUCT HIGHLIGHTS
1. 16-lead TSSOP and 16-lead SOIC_N available.
2. Pin compatible with the ADG508AKR and the
ADG509AKR devices.
3. 3 V, logic-compatible digital input where:
VIH = 2.0 V and VIL = 0.8 V.
4. VL logic power supply not required.
5. Low power consumption.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
©2006 Analog Devices, Inc. All rights reserved.
1 page  
ADG1308/ADG1309
SINGLE SUPPLY
VDD = 12 V, V ± 10%, VSS = 0 V, GND = 0 V, unless otherwise noted.1
Table 2.
Parameter
ANALOG SWITCH
Analog Signal Range
On Resistance, RON
On Resistance Match Between Channels, ∆RON
On Resistance Flatness, RFLAT (On)
LEAKAGE CURRENTS
Source Off Leakage, IS (Off )
+25ºC
325
500
10
20
65
±1
Drain Off Leakage, ID (Off )
±1
Channel On Leakage, ID, IS (On)
±1
DIGITAL INPUTS
Input High Voltage, VINH
Input Low Voltage, VINL
Input Current, IINL or IINH
±0.001
Digital Input Capacitance, CIN
DYNAMIC CHARACTERISTICS2
Transition Time, tTRANSITION
tON (EN)
tOFF (EN)
Break-Before-Make Time Delay, tBBM
3
100
170
90
110
105
130
45
Charge Injection
Off Isolation
Channel-to-Channel Crosstalk
−3 dB Bandwidth
CS (Off )
CD (Off )
ADG1308
ADG1309
CD, CS (On)
ADG1308
ADG1309
POWER REQUIREMENTS
IDD
2
80
80
500
5
10
15
20
15
0.002
IDD 220
VDD
−40ºC to +105ºC Unit
Test Conditions/Comments
0 to VDD
660
±50
±50
±50
V
Ω typ
Ω max
Ω typ
Ω max
Ω typ
nA typ
nA max
nA typ
nA max
nA typ
nA max
VS = 0 V to 10 V, IS = −1 mA; see Figure 13
VDD = 10.8 V, VSS = 0 V
VS = 0 V to 10 V, IS = −1 mA
VS = 3 V, 6 V, 9 V, IS = −1 mA
VDD = 13.2 V
VS = 1 V/10 V, VD = 10 V/1 V; see Figure 14
VS = 1 V/10 V, VD = 10 V/1 V; see Figure 14
VS = VD = 1 V or 10 V; see Figure 15
2.0 V min
0.8 V max
±0.1
μA max
pF typ
VIN = VINL or VINH
ns typ
RL = 300 Ω, CL = 35 pF
240 VS = 8 V; see Figure 16
ns typ
RL = 300 Ω, CL = 35 pF
170 VS = 8 V; see Figure 18
ns typ
RL = 300 Ω, CL = 35 pF
180 VS = 8 V; see Figure 18
ns typ
RL = 300 Ω, CL = 35 pF
20
ns min
VS1 = VS2 = 8 V; see Figure 17
pC typ
VS = 6 V, RS = 0 Ω, CL = 1 nF; see Figure 19
dB typ
RL = 50 Ω, CL = 5 pF, f = 1 MHz; see Figure 20
dB typ
RL = 50 Ω, CL = 5 pF, f = 1 MHz; see Figure 21
MHz typ
RL = 50 Ω, CL = 5 pF; see Figure 22
pF typ
f = 1 MHz, VS = 6 V
pF typ
pF typ
f = 1 MHz, VS = 6 V
f = 1 MHz, VS = 6 V
1.0
320
5/16.5
pF typ
pF typ
μA typ
μA max
μA typ
μA max
V min/V max
f = 1 MHz, VS = 6 V
f = 1 MHz, VS = 6 V
VDD = 13.2 V
Digital inputs = 0 V or VDD
Digital inputs = 5
VSS = 0 V, GND = 0 V
1 Temperature range for the B version is –40°C to +105°C.
2 Guaranteed by design; not subject to production test.
Rev. 0 | Page 5 of 16
5 Page 
ADG1308/ADG1309
TEST CIRCUITS
V
S
VS
D
IDS
Figure 13. On Resistance
IS (OFF)
AS
VS
ID (OFF)
DA
VD
Figure 14. Off Leakage
NC S
ID (ON)
DA
NC = NO CONNECT
VD
Figure 15. On Leakage
3V
ADDRESS
DRIVE (VIN)
0V
tTRANSITION
OUTPUT
50%
ttrf
<
<
20ns
20ns
50%
VIN
tTRANSITION
90%
90%
50Ω
2.4V
VDD
VSS
VDD
A0
A1
A2
VSS
S1
S2–S7
VS1
S8 VS8
ADG13081
OUTPUT
EN D
GND
300Ω
35pF
1SIMILAR CONNECTION FOR ADG1309.
Figure 16. Address to Output Switching Times, tTRANSITION
VDD
VSS
3V
ADDRESS
DRIVE (VIN)
0V
OUTPUT
80%
80%
tBBM
VIN 50Ω
VDD
A0
A1
A2
VSS
S1
S2–S7
VS
S8
ADG13081 OUTPUT
2.4V
EN
D
GND
300Ω
35pF
1SIMILAR CONNECTION FOR ADG1309.
Figure 17. Break-Before-Make Delay, tBBM
VDD
VSS
3V
ENABLE
DRIVE (VIN)
0V
50% 50%
VDD
A0
A1
A2
VSS
S1
S2–S8
VS
tON (EN)
OUTPUT
0.9VO
tOFF (EN)
0.9VO
VIN
ADG13081
OUTPUT
EN D
50Ω GND
300Ω
35pF
1SIMILAR CONNECTION FOR ADG1309.
Figure 18. Enable Delay, tON (EN), tOFF (EN)
Rev. 0 | Page 11 of 16
11 Page | ||
| Páginas | Total 16 Páginas | |
| PDF Descargar | [ Datasheet ADG1308.PDF ] | |
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