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Número de pieza | IC62LV2568LL | |
Descripción | 256K x 8 LOW POWER AND LOW Vcc CMOS STATIC RAM | |
Fabricantes | ICSI | |
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IICC626LV22L5V682L 568L
IICC626LV22L5V682LL568LL
256K x 8 LOW POWER and LOW V++
CMOS STATIC RAM
.EATURES
Access times of 55, 70, 100 ns
Low active power: 126 mW (max, L, LL)
Low standby power: 36 µW (max, L) and 7.2
µW (max, LL) CMOS standby
Low data retention voltage: 1.5V (min.)
Available in Low Power (-L) and Ultra-Low
Power (-LL)
Output Enable (OE) and two Chip Enable
TTL compatible inputs and outputs
Single 2.7V-3.6V power supply
Available in the 32-pin 8x20mm TSOP-1, 32-pin
8x13.4mm TSOP-1 and 48-pin 6*8mm T.-BGA
DESCRIPTION
The 1+51 IC62LV2568L and IC62LV2568LL are low power
and low VCC, 262,144-bit words by 8 bits CMOS static RAMs.
They are fabricated using 1+51's high-performance CMOS
technology. This highly reliable process coupled with innova-
tive circuit design techniques, yields higher performance and
low power consumption devices.
When CE1 is HIGH or CE2 is LOW (deselected), the device
assumes a standby mode at which the power dissipation can
be reduced by using CMOS input levels.
Easy memory expansion is provided by using two Chip Enable
inputs, CE1 and CE2. The active LOW Write Enable (WE)
controls both writing and reading of the memory.
The IC62LV2568L and IC62LV2568LL are available in 32-pin
8*20mm TSOP-1, 8*13.4mm TSOP-1 and 48-pin 6*8mm T.-
BGA.
.UNCTIONAL BLOCK DIAGRAM
A0-A17
VCC
GND
I/O0-I/O7
DECODER
I/O
DATA
CIRCUIT
2048 x 128 x 8
MEMORY ARRAY
COLUMN I/O
CE1
CE2
OE
WE
CONTROL
CIRCUIT
ICSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any errors
which may appear in this publication. © Copyright 2000, Integrated Circuit Solution Inc.
Integrated Circuit Solution Inc.
LPSR001-0A 05/01/2001
1
1 page IC62LV2568L
IC62LV2568LL
READ CYCLE SWITCHING CHARACTERISTICS(1) (Over Operating Range)
Symbol Parameter
tRC Read Cycle Time
tAA Address Access Time
tOHA Output Hold Time
tACE1 CE1 Access Time
tACE2 CE2 Access Time
tDOE OE Access Time
tLZOE(2) OE to Low-Z Output
tHZOE(2) OE to High-Z Output
tLZCE1(2) CE1 to Low-Z Output
tLZCE2(2) CE2 to Low-Z Output
tHZCE(2) CE1 or CE2 to Low-Z Output
-55
Min. Max.
55
55
10
55
55
30
5
20
10
10
0 20
-70
Min. Max.
70
70
10
70
70
35
5
0 25
10
10
0 25
-100
Min. Max.
100
100
15
100
100
50
5
0 30
10
10
0 30
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Notes:
1. Test conditions assume signal transition times of 5 ns or less, timing reference levels of 1.5V, input pulse levels
of 0.4V to 2.2V and output loading specified in .igure 1.
2. Tested with the load in .igure 2. Transition is measured ±500 mV from steady-state voltage. Not 100% tested.
AC TEST CONDITIONS
Parameter
Input Pulse Level
Input Rise and .all Times
Input and Output Timing
and Reference Level
Output Load
Unit
0.4V to 2.2V
5 ns
1.5V
See .igures 1 and 2
AC TEST LOADS
OUTPUT
1 TTL
100 pF
Including
jig and
scope
.igure 1
Integrated Circuit Solution Inc.
LPSR001-0A 05/01/2001
OUTPUT
1 TTL
5 pF
Including
jig and
scope
.igure 2
5
5 Page |
Páginas | Total 10 Páginas | |
PDF Descargar | [ Datasheet IC62LV2568LL.PDF ] |
Número de pieza | Descripción | Fabricantes |
IC62LV2568L | 256K x 8 LOW POWER AND LOW Vcc CMOS STATIC RAM | ICSI |
IC62LV2568LL | 256K x 8 LOW POWER AND LOW Vcc CMOS STATIC RAM | ICSI |
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