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PDF AD9992 Data sheet ( Hoja de datos )
| Número de pieza | AD9992 | |
| Descripción | 12-Bit CCD Signal Processor | |
| Fabricantes | Analog Devices | |
| Logotipo |  |
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12-Bit CCD Signal Processor with
Precision Timing Generator
AD9992
FEATURES
1.8 V AFETG core
Internal LDO regulator and charge pump circuitry
Compatibility with 3 V or 1.8 V systems
24 programmable vertical clock outputs
Correlated double sampler (CDS) with −3 dB, 0 dB,
+3 dB, and +6 dB gain
6 dB to 42 dB, 10-bit variable gain amplifier (VGA)
12-bit, 40 MHz ADC
Black level clamp with variable level control
Complete on-chip timing generator
Precision Timing core with 400 ps resolution
On-chip 3 V horizontal and RG drivers
General-purpose outputs (GPOs) for shutter and
system support
On-chip driver for external crystal
On-chip sync generator with external sync input
105-lead CSP_BGA package, 8 mm × 8 mm, 0.65 mm pitch
APPLICATIONS
Digital still cameras
GENERAL DESCRIPTION
The AD9992 is a highly integrated CCD signal processor for
digital still camera applications. It includes a complete analog
front end with analog to digital conversion combined with
a full-function programmable timing generator. The timing
generator is capable of supporting up to 24 vertical clock signals
to control advanced CCDs. A Precision Timing™ core allows
adjustment of high speed clocks with approximately 400 ps
resolution at 40 MHz operation. The AD9992 also contains
eight general-purpose inputs/outputs that can be used for
shutter and system functions.
The AD9992 is specified at pixel rates of up to 40 MHz. The
analog front end includes black level clamping, CDS, VGA, and
a 12-bit analog-to-digital converter (ADC). The timing generator
provides all the necessary CCD clocks: RG, H-clocks, V-clocks,
sensor gate pulses, substrate clock, and substrate bias control.
Operation is programmed using a 3-wire serial interface.
The AD9992 is specified over an operating temperature range
of −25°C to +85°C.
FUNCTIONAL BLOCK DIAGRAM
REFT REFB
CCDIN
CDS
6dB TO 42dB
VGA
VREF
12-BIT
ADC
AD9992
12
DOUT
–3dB, 0dB, +3dB, +6dB
3V INPUT
1.8V OUTPUT
LDO
REG
1.8V INPUT
3V OUTPUT
CHARGE
PUMP
RG
HL HORIZONTAL
8 DRIVERS
H1 TO H8
XV1 TO XV24
XSUBCK
24
VERTICAL
TIMING
CONTROL
8
CLAMP
INTERNAL CLOCKS
PRECISION
TIMING
GENERATOR
SYNC
GENERATOR
INTERNAL
REGISTERS
SL
SCK
SDATA
GPO1 TO GPO8
HD VD SYNC CLI CLO
Figure 1.
Rev. C
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113 ©2006–2007 Analog Devices, Inc. All rights reserved.
1 page  
AD9992
ANALOG SPECIFICATIONS
AVDD = 1.8 V, fCLI = 40 MHz, typical timing specifications, TMIN to TMAX, unless otherwise noted.
Table 3.
Parameter
CDS
Allowable CCD Reset Transient
CDS Gain Accuracy
−3.0 dB CDS Gain
0 dB CDS Gain
+3 dB CDS Gain
+6 dB CDS Gain
Maximum Input Range Before Saturation
−3 dB CDS Gain
0 dB CDS Gain
+3 dB CDS Gain
+6 dB CDS Gain
Allowable OB Pixel Amplitude (See Figure 2)
0 dB CDS Gain (Default)
+6 dB CDS Gain
VARIABLE GAIN AMPLIFIER (VGA)
Gain Control Resolution
Gain Monotonicity
Gain Range
Low Gain (VGA Code 15, Default)
Maximum Gain (VGA Code 1023)
BLACK LEVEL CLAMP
Clamp Level Resolution
Clamp Level
Minimum Clamp Level (Code 0)
Maximum Clamp Level (Code 1023)
ADC
Resolution
Differential Nonlinearity (DNL)
No Missing Codes
Integral Nonlinearity (INL)
Full-Scale Input Voltage
VOLTAGE REFERENCE
Reference Top Voltage (REFT)
Reference Bottom Voltage (REFB)
SYSTEM PERFORMANCE
Gain Accuracy
Low Gain (VGA Code 15)
Maximum Gain (VGA Code 1023)
Peak Nonlinearity, 1.0 V Input Signal
Total Output Noise
Power Supply Rejection (PSR)
Min Typ Max Unit
Test Conditions/Comments
0.5 0.8 V
−3.3 −2.8 −2.3 dB
−0.5 0
+0.5 dB
2.4 2.9 3.4 dB
5.0 5.5 6.0 dB
1.4 V p-p
1.0 V p-p
0.7 V p-p
0.5 V p-p
The limit is the lower of AVDD + 0.2 V or 2.2 V.
VGA gain = 6.3 dB (Code 15, default value).
VGA gain = 6.3 dB (Code 15, default value).
−100
−50
+200 mV
+100 mV
1024
Guaranteed
Steps
6.3 dB
42.4 dB
1024
0
255
Steps
LSB
LSB
Measured at ADC output.
12
−1.0 ±0.5 +1.0
Guaranteed
14
2.0
Bits
LSB
LSB
V
1.4 V
0.4 V
Includes entire signal chain.
0 dB CDS gain.
5.8 6.3 6.8 dB
Gain = (0.0358 × Code) + 5.76 dB.
41.9 42.4 42.9 dB
0.1 0.2 %
6 dB VGA gain, 0 dB CDS gain applied.
0.5 LSB rms AC-grounded input, 6 dB VGA gain applied.
50 dB Measured with step change on supply.
Rev. C | Page 5 of 92
5 Page 
TYPICAL PERFORMANCE CHARACTERISTICS
500
450
400 3.3V/1.8V
350
3.0V/1.8V
300
250 2.7V/1.8V
200
150
100
50
0
15 20 25 30 35 40
FREQUENCY (MHz)
Figure 4. Power vs. Frequency
(AVDD = TCVDD = DVDD = 1.8 V, All Other Supplies at 2.7 V, 3.0 V, or 3.3 V)
1.0
0.8
0.6
0.4
0.2
0
–0.2
–0.4
–0.6
–0.8
–1.0
0
500 1000 1500 2000 2500 3000 3500 4000
CODE
Figure 5. Typical Differential Nonlinearity (DNL) Performance
AD9992
150
+3dB CDS
0dB CDS
100 –3dB CDS
50
0
0 5 10 15 20 25 30 35 40
CDS + VGA GAIN (dB)
Figure 6. Output Noise vs. Total Gain (CDS + VGA)
45
5
4
3
2
1
0
–1
–2
0 500 1000 1500 2000 2500 3000 3500 4000
CODE
Figure 7. Typical Integral Nonlinearity (INL) Performance
Rev. C | Page 11 of 92
11 Page | ||
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| PDF Descargar | [ Datasheet AD9992.PDF ] | |
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