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Zarlink Semiconductor - (ZL50060 / ZL50061) 16 K-Channel Digital Switch

Numéro de référence ZL50061
Description (ZL50060 / ZL50061) 16 K-Channel Digital Switch
Fabricant Zarlink Semiconductor 
Logo Zarlink Semiconductor 





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ZL50061 fiche technique
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ZL50060/1
16 K-Channel Digital Switch with High Jitter
Tolerance, Per Stream Rate Conversion (2, 4, 8,
16, or 32 Mbps), and 64 Inputs and 64 Outputs
Data Sheet
Features
• 16,384-channel x 16,384-channel non-blocking
unidirectional switching.The Backplane and Local
inputs and outputs can be combined to form a
non-blocking switching matrix with 64 input
streams and 64 output streams
• 8,192-channel x 8,192-channel non-blocking
Backplane input to Local output stream switch
• 8,192-channel x 8,192-channel non-blocking
Local input to Backplane output stream switch
• 8,192-channel x 8,192-channel non-blocking
Backplane input to Backplane output switch
• 8,192-channel x 8,192-channel non-blocking
Local input to Local output stream switch
• Rate conversion on all data paths, Backplane-to-
Local, Local-to-Backplane, Backplane-to-
Backplane and Local-to-Local streams
• Backplane port accepts 32 input and 32 output
ST-BUS streams with data rates of 2.048 Mbps,
4.096 Mbps, 8.192 Mbps or 16.384 Mbps in any
combination, or a fixed allocation of 16 input and
16 output streams at 32.768 Mbps
• Local port accepts 32 input and 32 output ST-
BUS streams with data rates of 2.048 Mbps,
February 2006
Ordering Information
ZL50060GAC
ZL50060GAG2
ZL50061GAG
ZL50061GAG2
256 Ball PBGA
256 Ball PBGA**
272 Ball PBGA
272 Ball PBGA**
**Pb Free Tin/Silver/Copper
-40°C to +85°C
Trays
Trays
Trays
Trays
4.096 Mbps, 8.192 Mbps or 16.384 Mbps in any
combination, or a fixed allocation of 16 input and
16 output streams at 32.768 Mbps
• Exceptional input clock jitter tolerance (17 ns for
16 Mbps or lower data rates, 14 ns for 32 Mbps)
• Per-stream channel and bit delay for Local and
Backplane input streams
• Per-stream advancement for Local and Backplane
output streams
• Constant 2-frame throughput delay for frame
integrity
• Per-channel high impedance output control for
Local and Backplane streams
VDD_IO VDD_CORE
VSS (GND)
RESET
ODE
BSTi0-31
Backplane Data Memories
(8,192 channels)
Local
Interface
LSTi0-31
BSTo0-31
BCST0-3
BORS
FP8i
C8i
Backplane
Interface
Backplane
Connection Memory
(8,192 locations)
Local
Connection Memory
(8,192 locations)
Local
Interface
Input
Timing Unit
PLL
Local Data Memories
(8,192 channels)
Microprocessor Interface
and Internal Registers
Output
Timing
Unit
Test Port
LSTo0-31
LCST0-3
LORS
FP8o
FP16o
C8o
C16o
VDD_PLL
DS CS R/W A14-0 DTA D15-0 TMS TDi TDo TCK TRST
Figure 1 - ZL50060/1 Functional Block Diagram
1
Zarlink Semiconductor Inc.
Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc.
Copyright 2003-2006, Zarlink Semiconductor Inc. All Rights Reserved.

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