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Zarlink Semiconductor - Flexible 512-ch Digital Switch

Numéro de référence ZL50012
Description Flexible 512-ch Digital Switch
Fabricant Zarlink Semiconductor 
Logo Zarlink Semiconductor 





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ZL50012 fiche technique
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ZL50012
Flexible 512-ch Digital Switch
Data Sheet
Features
• 512 channel x 512 channel non-blocking switch at
2.048 Mb/s, 4.096 Mb/s or 8.192 Mb/s operation
• Rate conversion between the ST-BUS inputs and
ST-BUS outputs
• Per-stream ST-BUS input with data rate selection
of 2.048 Mb/s, 4.096 Mb/s or 8.192 Mb/s
• Per-stream ST-BUS output with data rate
selection of 2.048 Mb/s, 4.096 Mb/s or
8.192 Mb/s; the output data rate can be different
than the input data rate
• Per-stream high impedance control output for
every ST-BUS output with fractional bit
advancement
• Per-stream input channel and input bit delay
programming with fractional bit delay
• Per-stream output channel and output bit delay
programming with fractional bit advancement
• Multiple frame pulse outputs and reference clock
outputs
• Per-channel constant throughput delay
July 2004
Ordering Information
ZL50012/QCC
ZL50012/GDC
160 Pin LQFP
144 Ball LBGA
-40°C to +85°C
• Per-channel high impedance output control
• Per-channel message mode
• Per-channel pseudo random bit sequence
(PRBS) pattern generation and bit error detection
• Control interface compatible to Motorola non-
multiplexed CPUs
• Connection memory block programming
capability
• IEEE-1149.1 (JTAG) test port
• 3.3V I/O with 5 V tolerant input
VDD
VSS
RESET
ODE
STi0-15
S/P Converter
Data Memory
P/S Converter
STo0-15
Output HiZ Control
STOHZ0-15
FPi Connection Memory
CKi Input Timing
FPo0
APLL
Microprocessor
Interface
and
Internal
Registers
Output Timing
CKo0
FPo1
CKo1
FPo2
CKo2
Test Port
IC0 - 4
CLKBYPS
ICONN0 - 2
Figure 1 - ZL50012 Functional Block Diagram
1
Zarlink Semiconductor Inc.
Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc.
Copyright 2002-2004, Zarlink Semiconductor Inc. All Rights Reserved.

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