PDF NX25F041B Data sheet ( Hoja de datos )

Número de pieza	NX25F041B
Descripción	(NX25F011B - NX25F041B) SERIAL FLASH MEMORIES
Fabricantes	NexFlash
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No Preview Available ! www.DataSheet4U.com PRELIMINARY DECEMBER 2001 NX25F011B, NX25F021B, NX25F041B 1M-BIT, 2M-BIT, AND 4M-BIT SERIAL FLASH MEMORIES WITH 4-PIN SPI INTERFACE This document contains PRELIMINARY INFORMATION. NexFlash reserves the right to make changes to its product at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any errors which may appear in this publication.  Copyright 2001, NexFlash Technologies, Inc. NexFlash Technologies, Inc. PRELIMINARY NXSF016F-1201 12/12/01 © 1 1 page NX25F011B NX25F021B NX25F041B FUNCTIONAL OVERVIEW An architectural block diagram of the NX25F011B, NX25F021B, and NX25F041B is shown in Figure 2. Key elements of the architecture include: • SPI Interface and Command Set Logic • Serial Flash Memory Array • Serial SRAM and Program Buffer • Write Protection Logic • Configuration and Status Registers • Device Information Sector Pin Descriptions 1Package The NX25F011B, NX25F021B, and NX25F041B are available in a 28-pin TSOP (Type I) surface mount package. The NX25F011B and NX25F021B are available in either an 28-pin SOIC and a 14-pin TSOP package (contact NexFlash for information on the 14-pin TSOP package). The NX25F041B is also available in a 28-pin SOIC package. See Figure 3A, 3B and Table 1 for pin assignments. All interface and supply pins are on one side of the TSOP 3package. The “No Connect” (NC) pins are not connected to the device, allowing the pads and the area around them to be used for routing PCB system traces. The devices are also available in a cost-effective and space-efficient removable Serial Flash Module package. 4 DEVICE INFORMATION SECTOR (DIS) (READ ONLY) WP HOLD OR R/B WRITE CONTROL LOGIC HOLD OR READ/BUSY LOGIC NexFlash 1, 2 AND 4 M-BIT SERIAL FLASH MEMORY ARRAY 16 512, 1024 AND 2048 BYTE-ADDRESSABLE SECTORS OF 264 BYTES EACH ORGANIZED IN 16, 32, AND 64 BLOCKS OF 32 SECTORS PER BLOCK CONFIGURATION REGISTER STATUS REGISTER HIGH-VOLTAGE GENERATORS 2112 SRAM (264 BYTES) SCK CS SI SO SPI COMMAND AND CONTROL LOGIC SECTOR-ADDRESS LATCH DATA BYTE-ADDRESS LATCH/COUNTER 88 8 COLUMN DECODE, SENSE AMP LATCH AND DATA COMPARE LOGIC 9 Figure 2. NX25F011B, NX25F021B, and NX25F041B Architectural Block Diagram 5 6 7 8 9 10 11 12 NexFlash Technologies, Inc. PRELIMINARY NXSF016F-1201 12/12/01 © 5 5 Page NX25F011B NX25F021B NX25F041B Table 2A. Write Protect Range Sector Selection (Hex) Write Protect Range Config. Bits WR3 WR2 WR1 WR0 00 00 00 00 00 01 01 01 01 10 10 10 10 11 11 11 01 10 11 00 01 10 11 00 01 10 11 00 01 10 11 11 (NX25F011B) Write Protected Sectors WD=0 WD=1 None None 000 - 01FH 000 - 03FH 000 - 05FH 000 - 07FH 000 - 09FH 000 - 0BFH 000 - 0DFH 000 - 0FFH 000 - 11FH 000 - 13FH 000 - 15FH 000 - 17FH 000 - 19FH 000 - 1BFH 1 E0 - 1FF 1 C0 - 1FF 1 A0 - 1FF 1 80 - 1FF 1 60 - 1FF 1 40 - 1FF 1 20 - 1FF 1 00 - 1FF 0 E0 - 1FF 0 C0 - 1FF 0 A0 - 1FF 0 80 - 1FF 0 60 - 1FF 0 40 - 1FF ALL ALL Table 2C. Write Protect Range Sector Selection (Hex) Write Protect Range Config. Bits WR3 WR2 WR1 WR0 00 00 00 00 01 01 01 01 10 10 00 01 10 11 00 01 10 11 00 01 10 10 11 10 11 00 11 11 01 10 11 11 (NX25F041B) Write Protected Sectors WD=0 WD=1 None 000 - 01FH 000 - 03FH 000 - 05FH 000 - 07FH 000 - 09FH 000 - 0BFH 000 - 0DFH 000 - 0FFH 000 - 11FH None 7 E0 - 7FFH 7 C0 - 7FFH 7 A0 - 7FFH 7 80 - 7FFH 7 60 - 7FFH 7 40 - 7FFH 7 20 - 7FFH 7 00 - 7FFH 6 E0 - 7FFH 000 - 13FH 000 - 15FH 000 - 17FH 6 C0 - 7FFH 6 A0 - 7FFH 6 80 - 7FFH 000 - 19FH 000 - 1BFH 6 60 - 7FFH 6 40 - 7FFH ALL ALL 1 2 3 4 5 6 Table 2B. Write Protect Range Sector Selection (Hex) Write Protect Range Config. Bits WR3 WR2 WR1 WR0 00 00 00 00 01 10 00 01 01 11 00 01 01 01 10 10 11 00 10 10 10 01 10 11 11 11 11 00 01 10 11 11 (NX25F021B) Write Protected Sectors WD=0 WD=1 None None 000 - 01FH 000 - 03FH 3 E0 - 3FF 3 C0 - 3FF 000 - 05FH 000 - 07FH 000 - 09FH 3 A0 - 3FF 3 80 - 3FF 3 60 - 3FF 000 - 0BFH 000 - 0DFH 000 - 0FFH 3 40 - 3FF 3 20 - 3FF 3 00 - 3FF 000 - 11FH 000 - 13FH 000 - 15FH 2 E0 - 3FF 2 C0 - 3FF 2 A0 - 3FF 000 - 17FH 000 - 19FH 000 - 1BFH 2 80 - 3FF 2 60 - 3FF 2 40 - 3FF ALL ALL 7HOLD-R/B, HR[1:0] The Hold-Ready/Busy (HOLD-R/B) bits HR1 and HR0 are located at bits CF[1:0] of the configuration register. These two bits select one of four possible functions: No Connect, 8HOLD input, R/B Output, or R/B Output with open drain. The factory setting for the pin is “No Connect”. HR1 HR0 Pin Configuration 0 0 HOLD input 9 0 1 No Connect 1 0 R/B Output (Open Drain) 1 1 R/B Output 10 Configured as a R/B output, the pin can serve as a system interrupt. When R/B is high, the array is ready to be programmed. When R/B is low, it is busy programming. If 1 1configured with an open-drain, an external pull-up resistor should be used. As a HOLD input, the pin can be used in conjunction with 1 2the CS and SCK pin to suspend a serial command sequence without resetting the command. This can be useful if a command is in process and a higher priority task on the same SPI bus needs to be attended to. To NexFlash Technologies, Inc. PRELIMINARY NXSF016F-1201 12/12/01 © 11 11 Page

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