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Número de pieza NLAST9431
Descripción Low Voltage Single Supply Dual DPDT Analog Switch
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NLAST9431
Low Voltage Single Supply
Dual DPDT Analog Switch
The NLAST9431 is an advanced CMOS dual−independent DPDT
(double pole−double throw) analog switch, fabricated with silicon
gate CMOS technology. It achieves high−speed propagation delays
and low ON resistances while maintaining CMOS low−power
dissipation. This DPDT controls analog and digital voltages that may
vary across the full power−supply range (from VCC to GND).
The device has been designed so the ON resistance (RON) is much
lower and more linear over input voltage than RON of typical CMOS
analog switches.
The channel−select input structure provides protection when
voltages between 0 V and 5.5 V are applied, regardless of the supply
voltage. This input structure helps prevent device destruction caused
by supply voltage − input/output voltage mismatch, battery backup,
hot insertion, etc.
The NLAST9431 can also be used as a quad 2−to−1 multiplexer−
demultiplexer analog switch with two Select pins that each controls
two multiplexer−demultiplexers.
Select Pins Compatible with TTL Levels
Channel Select Input Overvoltage Tolerant to 5.5 V
Fast Switching and Propagation Speeds
Break−Before−Make Circuitry
Low Power Dissipation: ICC = 2 mA (Max) at TA = 25°C
Diode Protection Provided on Channel Select Input
Improved Linearity and Lower ON Resistance over Input Voltage
Latch−up Performance Exceeds 300 mA
Chip Complexity: 158 FETs
Pb−Free Packages are Available
http://onsemi.com
WQFN16
CASE 488AP
MARKING
DIAGRAMS
1ÎÎ16ÎÎ
BB M
G
BB = Specific Device Code
M = Date Code & Assembly Location
G = Pb−Free Device
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 10 of this data sheet.
© Semiconductor Components Industries, LLC, 2006
January, 2006 − Rev. 0
1
Publication Order Number:
NLAST9431/D

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NLAST9431
AC ELECTRICAL CHARACTERISTICS (Input tr = tf = 3.0 ns)
Symbol
Parameter
tON Turn−On Time
(Figures 12 and 13)
Test Conditions
RL = 300 W, CL = 35 pF
(Figures 5 and 6)
tOFF Turn−Off Time
(Figures 12 and 13)
RL = 300 W, CL = 35 pF
(Figures 5 and 6)
tBBM
Minimum Break−Before−Make VIS = 3.0 V (Figure 4)
Time
RL = 300 W, CL = 35 pF
VCC VIS
(V) (V)
2.5 2.0
3.0 2.0
4.5 3.0
5.5 3.0
2.5 2.0
3.0 2.0
4.5 3.0
5.5 3.0
2.5 2.0
3.0 2.0
4.5 3.0
5.5 3.0
Guaranteed Maximum Limit
*555C to 255C
t855C t1255C
Min Typ* Max Min Max Min Max Unit
5 23 35 5 38 5 41 ns
5 16 24 5 27 5 30
2 11 16 2 19 2 22
2 9 14 2 17 2 20
1 7 12 1 15 1 18 ns
1 5 10 1 13 1 16
1 4 6 1 9 1 12
1 3 5 1 8 1 11
1 12
1 11
16
15
1 1 ns
11
11
11
*Typical Characteristics are at 25°C.
CIN
CNO or CNC
CCOM
C(ON)
Maximum Input Capacitance, Select Input
Analog I/O (Switch Off)
Common I/O (Switch Off)
Feedthrough (Switch On)
Typical @ 25, VCC = 5.0 V
8
10
10
20
pF
ADDITIONAL APPLICATION CHARACTERISTICS (Voltages Referenced to GND Unless Noted)
Symbol
Parameter
Condition
VCC Typical
V 255C Unit
BW Maximum On−Channel *3 dB Bandwidth or VIN = 0 dBm
Minimum Frequency Response
VIN centered between VCC and GND
(Figure 11)
(Figure 7)
3.0 145 MHz
4.5 170
5.5 175
VONL
Maximum Feedthrough On Loss
VIN = 0 dBm @ 100 kHz to 50 MHz
VIN centered between VCC and GND
(Figure 7)
3.0 −3 dB
4.5 −3
5.5 −3
VISO
Off−Channel Isolation
(Figure 10)
f = 100 kHz; VIS = 1 V RMS
VIN centered between VCC and GND
(Figure 7)
3.0 −93 dB
4.5 −93
5.5 −93
Q
THD
Charge Injection Select Input to Common I/O
(Figure 15)
VIN = VCC to GND, FIS = 20 kHz
tr = tf = 3 ns
RIS = 0 W, CL = 1000 pF
Q = CL * DVOUT (Figure 8)
3.0 1.5 pC
5.5 3.0
Total Harmonic Distortion
THD ) Noise
(Figure 14)
FIS = 20 Hz to 100 kHz, RL = Rgen = 600 W,
CL = 50 pF
%
VIS = 5.0 VPP sine wave
5.5 0.1
VCT
Channel to Channel Crosstalk
f = 100 kHz; VIS = 1 V RMS
VIN centered between VCC and GND
(Figure 7)
dB
5.5 −90
3.0 −90
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NLAST9431
PACKAGE DIMENSIONS
WQFN16
MN SUFFIX
CASE 488AP−01
ISSUE A
PIN 1 REFERENCE
D
ÏÏÏÏÏÏÏÏ
A
E
2X 0.15 C
2X 0.15 C
B
0.10 C
0.08 C
A
15 X L
5
4
A1
A3
8
9
SEATING
PLANE
C
1
16
L1
e
12
16 X 0.10 C A B
b
0.05 C NOTE 3
NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME
Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS
3. DIMENSION b APPLIES TO PLATED TERMINAL
AND IS MEASURED BETWEEN 0.25 AND 0.30 MM
FROM TERMINAL.
4. COPLANARITY APPLIES TO THE EXPOSED PAD
AS WELL AS THE TERMINALS.
5. EXPOSED PADS CONNECTED TO DIE FLAG.
USED AS TEST CONTACTS.
MILLIMETERS
DIM MIN MAX
A 0.70 0.80
A1 0.00 0.050
A3 0.20 REF
b 0.15 0.25
D 1.80 BSC
E 2.60 BSC
e 0.40 BSC
L 0.30 0.50
L1 0.40 0.60
MOUNTING FOOTPRINT
0.562
0.0221
0.400
0.0157
2.900
0.1142
1
1.200
0.0472
0.225
0.0089
0.463
0.0182
2.100
0.0827
ǒ ǓSCALE 20:1
mm
inches
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any
liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental
damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over
time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under
its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body,
or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death
may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees,
subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of
personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part.
SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
LITERATURE FULFILLMENT:
Literature Distribution Center for ON Semiconductor
P.O. Box 61312, Phoenix, Arizona 85082−1312 USA
Phone: 480−829−7710 or 800−344−3860 Toll Free USA/Canada
Fax: 480−829−7709 or 800−344−3867 Toll Free USA/Canada
N. American Technical Support: 800−282−9855 Toll Free
USA/Canada
Japan: ON Semiconductor, Japan Customer Focus Center
2−9−1 Kamimeguro, Meguro−ku, Tokyo, Japan 153−0051
Phone: 81−3−5773−3850
http://onsemi.com
11
ON Semiconductor Website: http://onsemi.com
Order Literature: http://www.onsemi.com/litorder
For additional information, please contact your
local Sales Representative.
NLAST9431/D

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