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PDF NLAS9431 Data sheet ( Hoja de datos )
| Número de pieza | NLAS9431 | |
| Descripción | Low Voltage Single Supply Dual DPDT Analog Switch | |
| Fabricantes | ON Semiconductor | |
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NLAS9431
Low Voltage Single Supply
Dual DPDT Analog Switch
The NLAS9431 is an advanced dual−independent CMOS double
pole−double throw (DPDT) analog switch fabricated with silicon
gate CMOS technology. It achieves high speed propagation delays
and low ON resistances while maintaining CMOS low power
dissipation. This DPDT controls analog and digital voltages that may
vary across the full power−supply range (from VCC to GND).
The device has been designed so the ON resistance (RON) is much
lower and more linear over input voltage than RON of typical CMOS
analog switches.
The channel select input is compatible with standard CMOS outputs.
The channel select input structure provides protection when
voltages between 0 V and 5.5 V are applied, regardless of the supply
voltage. This input structure helps prevent device destruction caused
by supply voltage − input/output voltage mismatch, battery backup,
hot insertion, etc.
The NLAS9431 can also be used as a quad 2−to−1 multiplexer−
demultiplexer analog switch with two Select pins that each controls
two multiplexer−demultiplexers.
• Direct Battery Connection
• Channel Select Input Over−Voltage Tolerant to 5.5 V
• Fast Switching and Propagation Speeds
• Break−Before−Make Circuitry
• Low Power Dissipation: ICC = 2 mA (Max) at TA = 25°C
• Diode Protection Provided on Channel Select Input
• Improved Linearity and Lower ON Resistance over Input Voltage
• Latch−up Performance Exceeds 300 mA
• Chip Complexity: 158 FETs
• 16−Lead WQFN Package, 1.8 mm x 2.6 mm
• This is a Pb−Free Device
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WQFN16
CASE 488AP
MARKING
DIAGRAMS
ÎÎ16
1
BA M
G
BA = Specific Device Code
M = Date Code & Assembly Location
G = Pb−Free Device
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 10 of this data sheet.
© Semiconductor Components Industries, LLC, 2006
January, 2006 − Rev. 0
1
Publication Order Number:
NLAS9431/D
1 page  
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NLAS9431
AC ELECTRICAL CHARACTERISTICS (Input tr = tf = 3.0 ns)
Guaranteed Maximum Limit
Symbol
Parameter
Test Conditions
VCC VIS *555C to 255C
t855C
t1255C
(V) (V) Min Typ* Max Min Max Min Max Unit
tON Turn−On Time
(Figures 12 and 13)
RL = 300 W, CL = 35 pF 2.5 2.0 5 23 35 5 38 5 41 ns
(Figures 5 and 6)
3.0 2.0 5 16 24 5 27 5 30
4.5 3.0 2 11 16 2 19 2 22
5.5 3.0 2 9 14 2 17 2 20
tOFF Turn−Off Time
(Figures 12 and 13)
RL = 300 W, CL = 35 pF 2.5 2.0
(Figures 5 and 6)
3.0 2.0
4.5 3.0
5.5 3.0
1
1
1
1
7 12 1 15 1 18 ns
5 10 1 13 1 16
4 6 1 9 1 12
3 5 1 8 1 11
tBBM
Minimum Break−Before−Make
RL = 300 W, CL = 35 pF 2.5 2.0 1 12
1
1
ns
Time
(Figure 4)
3.0 2.0 1 11 1 1
4.5 3.0 1 6 1 1
5.5 3.0 1 5 1 1
CIN
CNO or CNC
CCOM
C(ON)
Maximum Input Capacitance, Select Input
Analog I/O (switch off)
Common I/O (switch off)
Feedthrough (switch on)
*Typical Characteristics are at 25°C.
Typical @ 25, VCC = 5.0 V
8
10
10
20
pF
ADDITIONAL APPLICATION CHARACTERISTICS (Voltages Referenced to GND Unless Noted)
Symbol
Parameter
BW Maximum On−Channel −3dB
Bandwidth or Minimum Frequency
Response (Figure 11)
VONL Maximum Feedthrough On Loss
VISO Off−Channel Isolation (Figure 10)
Q Charge Injection Select Input to
Common I/O (Figure 15)
THD
VCT
Total Harmonic Distortion THD +
Noise (Figure 14)
Channel−to−Channel Crosstalk
Condition
VIS = 0 dBm
VIS centered between VCC and GND
(Figure 7)
VIS = 0 dBm @ 100 kHz to 50 MHz
VIS centered between VCC and GND
(Figure 7)
f = 100 kHz; VIS = 1 V RMS
VIS centered between VCC and GND
(Figure 7)
VIS = VCC to GND, FIN = 20 kHz
tr = tf = 3 ns
RIS = 0 W, CL = 1000 pF
Q = CL * DVOUT
(Figure 8)
FIN = 20 Hz to 100 kHz, RL = Rgen = 600 W, CL = 50 pF
VIS = 5.0 VPP sine wave
f = 100 kHz; VIS = 1 V RMS
VIS centered between VCC and GND
(Figure 7)
VCC Typical
V 255C Unit
3.0 145 MHz
4.5 170
5.5 175
3.0 −3 dB
4.5 −3
5.5 −3
3.0 −93 dB
4.5 −93
5.5 −93
pC
3.0 1.5
5.5 3.0
%
5.5 0.1
dB
5.5 −90
3.0 −90
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5
5 Page 
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NLAS9431
PACKAGE DIMENSIONS
WQFN16
MN SUFFIX
CASE 488AP−01
ISSUE A
PIN 1 REFERENCE
D
ÏÏÏÏÏÏÏÏ
A
E
2X 0.15 C
2X 0.15 C
B
0.10 C
0.08 C
A
15 X L
5
4
A1
A3
8
9
SEATING
PLANE
C
1
16
L1
e
12
16 X 0.10 C A B
b
0.05 C NOTE 3
NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME
Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS
3. DIMENSION b APPLIES TO PLATED TERMINAL
AND IS MEASURED BETWEEN 0.25 AND 0.30 MM
FROM TERMINAL.
4. COPLANARITY APPLIES TO THE EXPOSED PAD
AS WELL AS THE TERMINALS.
5. EXPOSED PADS CONNECTED TO DIE FLAG.
USED AS TEST CONTACTS.
MILLIMETERS
DIM MIN MAX
A 0.70 0.80
A1 0.00 0.050
A3 0.20 REF
b 0.15 0.25
D 1.80 BSC
E 2.60 BSC
e 0.40 BSC
L 0.30 0.50
L1 0.40 0.60
MOUNTING FOOTPRINT
0.562
0.0221
0.400
0.0157
2.900
0.1142
1
1.200
0.0472
0.225
0.0089
0.463
0.0182
2.100
0.0827
ǒ ǓSCALE 20:1
mm
inches
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any
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damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over
time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under
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PUBLICATION ORDERING INFORMATION
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11
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For additional information, please contact your
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NLAS9431/D
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| Páginas | Total 11 Páginas | |
| PDF Descargar | [ Datasheet NLAS9431.PDF ] | |
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