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PDF SCAN12100 Data sheet ( Hoja de datos )
| Número de pieza | SCAN12100 | |
| Descripción | CPRI SerDes | |
| Fabricantes | National Semiconductor | |
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November 2006
SCAN12100
1228.8 and 614.4 Mbps CPRI SerDes with Auto RE Sync and
Precision Delay Calibration Measurement
General Description
The SCAN12100 is a 1228.8 and 614.4 Mbps serializer/de-
seralizer (SerDes) for high-speed bidirectional serial data
transmission over FR-4 printed circuit board backplanes, bal-
anced cables, and optical fiber. The SCAN12100 integrates
precision delay calibration measurement (DCM) circuitry that
measures link delay components to better than ± 800 ps ac-
curacy.
The SCAN12100 features independent transmit and receive
PLLs, on-chip oscillator, and intelligent clock management
circuitry to automatically perform remote radio head synchro-
nization and reduce the cost and complexity of external clock
networks.
The SCAN12100 is programmable though an MDIO interface
as well as through pins, featuring configurable transmitter de-
emphasis, receiver equalization, speed rate selection, inter-
nal pattern generation/verification, and loop back modes. In
addition to at-speed BIST, the SCAN12100 includes IEEE
1149.1 and 1149.6 testability.
Note: For a full SCAN12100 datasheet please contact
your local National Semiconductor representitive
Features
■ Exceeds LV and HV CPRI voltage and jitter requirements
■ 1228.8, and 614.4 Mbps operation
■ Pin and package compatibility with the SCAN25100
■ Integrated delay calibration measurement (DCM) directly
measures T14 and Toffset delays to ≤ ± 800 ps
■ DCM also measures chip and other delays to ≤ ± 1200 ps
accuracy
■ Deterministic chip latency
■ Automatic receiver lock and RE synchronization without
reference clock or external crystal
■ Independent transmit and receive PLLs for seamless RE
synchronization
■ Low noise recovered clock output
■ Requires no jitter cleaning in single-hop applications
■ >8 kV ESD on the CML IO, >7 kV on all other pins, >2 kV
CDM
■ Hot plug protection
■ LOS, LOF, 8b/10b line code violation, comma, and
receiver PLL lock reporting
■ Programmable hyperframe length and start of hyperframe
character
■ Programmable transmit de-emphasis and receive
equalization with on-chip termination
■ Advanced testability features
— IEEE 1149.1 and 1149.6
— At-speed BIST pattern generator/verifier
— Multiple loopback modes
■ 1.8V or 3.3V compatible parallel bus interface
■ 100-pin TQFP package with exposed dap
■ Industrial –40 to +85° C temperature range
Block Diagram
© 2006 National Semiconductor Corporation 202095
20209542
www.national.com
1 page  
Pin #
96
97
Pin Name
SPMODE [0]
SPMODE [1]
98 TENBMODE
99 LOOP [0]
100 LOOP [1]
MDC/MDIO
30 MDC
31 MDIO
37 ADD0
36 ADD1
35 ADD2
34 ADD3
33 ADD4
IEEE 1149.1 (JTAG)
45 TDI
41 TDO
44 TMS
43 TCK
46 TRSTB
RESERVED PINS
83 RES1
84 RES2
POWER
9, 15, 20, AVDD18
32, 38, 47,
85
8, 14, 21, AVDD33
42
1, 2, 28, 29 PVDD33
50, 51, 76, IOVDD
87
GROUND
3, 4, 5, 10, GND
13, 16, 19,
24, 25, 26,
27, 39, 40,
48, 49, 63,
75, 86
I/O, Type
Description
I, LVTTL or 1.8V Speed mode configuration. (OPMODE must be low)
LVCMOS Internal Pulling both pins low enables MDIO control.
pull down
SPMODE [1] SPMODE [0]
0 0 Rate selected via MDIO
0 1 614.4 Mbps rate mode
1 0 1228.8 Mbps rate mode
1 1 Reserved
I, LVTTL or 1.8V Enable 10-bit mode
LVCMOS, Internal The 8B/10B specification is defined in IEEE 802.3-2000 section 36.2.2
pull down
0 = Selects 8-bit mode. Enables the internal 8b/10b encoder and decoder.
1 = Selects 10-bit mode. Bypasses internal 8b/10b encoder and decoder.
I, LVTTL or 1.8V Loop back configuration.
LVCMOS, Internal Pulling both pins low enables MDIO control.
pull down
Note: During Special line (remote) loop back mode, the output de-emphasis control
is disabled.
LOOP [1]
LOOP [0]
0 0 Normal mode—no loop back
0 1 Line (remote) loop back mode
1 0 Local loop back mode
1 1 Special line (remote) loop back mode
3.3V LVTTL MDC/MDIO configuration bus.
Internal pull up on Protocol per IEEE 802.2ae-2002 MDC/MDIO Clause 45. These pins are 3.3V LVTTL
ADDR pins compatible, not 1.2V signal compatible.
3.3V LVTTL JTAG test bus for IEEE 1149.1 and 1149.6 support.
Internal pull up on
TDI, TMS, and
TRSTB
I
I, Power
Reserved.
Tie with 5 KΩ resistor to ground.
1.8V analog supply.
I, Power
I, Power
I, Power
I, Ground
3.3V analog supply.
3.3V PLL supply (minimize supply noise to < 100 mV peak-to-peak).
1.8V or 3.3V parallel I/O bus and control pin supply.
See VSEL pin description for additional information.
Device ground.
5 www.national.com
5 Page 
AC Timing Diagrams
READ MODE
WRITE MODE
20209509
20209510
11 www.national.com
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| PDF Descargar | [ Datasheet SCAN12100.PDF ] | |
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