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PDF NBSG111BAEVB Data sheet ( Hoja de datos )
| Número de pieza | NBSG111BAEVB | |
| Descripción | Evaluation Board Manual | |
| Fabricantes | ON Semiconductor | |
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NBSG111BAEVB
Evaluation Board Manual
for NBSG111
http://onsemi.com
EVALUATION BOARD MANUAL
DESCRIPTION
This document describes the NBSG111 evaluation board
and the appropriate lab test setups. It should be used in
conjunction with the NBSG111 data sheet which contains
full technical details on the device specifications and
operation.
The evaluation board is designed to facilitate a quick
evaluation of the NBSG111 GigaComm™ 1:10 clock data
driver. The NBSG111 allows selection between two inputs
and fan out 10 identical differential outputs. The Reduced
Swing ECL (RSECL) output ensures minimal noise and fast
switching edges.
The evaluation board is implemented in two layers for
higher performance. For standard lab setup and test, a split
(dual) power supply is required enabling the 50 W
impedance from the scope to be used as termination of the
ECL signals (VTT = VCC – 2.0 V, in split power supply setup,
VTT is the system ground).
What measurements can you expect to make?
With this evaluation board, the following measurements
could be performed in single−ended(1) or differential modes
of operation:
• Jitter
• Output Skew
• Gain/Return Loss
• Eye Pattern Generation
• Frequency Performance
• Output Rise and Fall Time
• VIHCMR (Input High Common Mode Range)
1. Single−ended measurements can only be made at
VCC − VEE = 3.3 V using this board setup.
Figure 1. NBSG111 Evaluation Board
© Semiconductor Components Industries, LLC, 2003
October, 2003 − Rev. 0
1
Publication Order Number:
NBSG111BAEVB/D
1 page  
NBSG111BAEVB
Setup Test Configurations For Differential Operation
Small Signal Setup
Step 2:
Step 3:
Input Setup
2a: Calibrate VNA from 1.0 GHz to 12 GHz.
2b: Set input level to –35 dBm at the output of the 180° Hybrid coupler (input of the DUT).
Output Setup
3a: Set display to measure S21 and record data.
Large Signal Setup
Step 2:
Step 3:
Input Setup
2a: Calibrate VNA from 1.0 GHz to 12 GHz.
2b: Set input levels to −2.0 dBm (500 mV) at the input of DUT.
Output Setup
3a: Set display to measure S21 and record data.
PORT 1
Vector Network Analyzer
PORT 2
GND
50 W
VCC = 2.0 V
VCC
Float
VTT = 0 V
VCC SEL SEL
CLK0
GND
Q0
GND
50 W
Bias T
1805 Hybrid
Coupler
Q0 50 W
CLK0
VEE
Q9
EN
EN
GND
Q9
GND
50 W
GND
50 W
NOTE:
VEE = −1.3 V (3.3 V op)
VTT = 0 V
GND
* Q0 − Q9 Outputs
VCC Float
All differential cable pairs must be matched.
Due to simplifcation of the block diagram CLK1/CLK1 and Q1 − Q8 connections are not shown.
Figure 4. NBSG111 Board Setup – Frequency Domain (Differential Mode)
http://onsemi.com
5
5 Page 
NBSG111BAEVB
PACKAGE DIMENSIONS
FCBGA−49
BA SUFFIX
PLASTIC 8x8 mm (1.0 mm pitch) BGA FLIP CHIP PACKAGE
CASE 489A−02
ISSUE A
A
BD
ÉÉÉÉTERMINAL A1 CORNER
E
A
A2
Z
4X
0.15 C
D1
e
DETAIL A
Z
FEDUCIAL FOR PIN A1
IDENTIFICATION IN THIS AREA
NOTES:
1. CONTROLLING DIMENSION: MILLIMETER.
2. DIMENSIONS AND TOLERANCES PER ASME
Y14.5M−1994.
3. DIMENSION b IS MEASURED AT THE MAXIMUM
SOLDER BALL DIAMETER, PARALLEL TO DATUM
PLANE C.
4. DATUM C (SEATING PLANE) IS DEFINED BY THE
SPHERICAL CROWNS OF THE SOLDER BALLS.
5. PARALLELISM MEASUREMENT SHALL EXCLUDE
ANY EFFECT OF MARK ON TOP SURFACE OF
PACKAGE.
6. 489A−01 OBSOLETE, NEW STANDARD 489A−02.
MILLIMETERS
DIM MIN MAX
A −−− 1.40
A1 0.3 0.5
A2 0.91 REF
b 0.40 0.60
D 8.00 BSC
D1 6.00 BSC
E 8.00 BSC
E1 6.00 BSC
e 1.00 BSC
e
E1
A
B 49 X b NOTE 3
C 0.15 M C A B
D 0.08 M C
NOTE 5
0.20 C
NOTE 4 C
7 65 43 21
VIEW Z−Z
E
F
G
SEATING
PLANE
0.12 C
A1
49 X
DETAIL A
(ROTATED 90_ C.W.)
http://onsemi.com
11
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| Páginas | Total 12 Páginas | |
| PDF Descargar | [ Datasheet NBSG111BAEVB.PDF ] | |
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