|
|
PDF AD8196 Data sheet ( Hoja de datos )
| Número de pieza | AD8196 | |
| Descripción | 2:1 HDMI/DVI Switch | |
| Fabricantes | Analog Devices | |
| Logotipo |  |
|
Hay una vista previa y un enlace de descarga de AD8196 (archivo pdf) en la parte inferior de esta página. Total 25 Páginas | ||
|
No Preview Available !
2:1 HDMI/DVI Switch with Equalization
AD8196
FEATURES
Two inputs, one output HDMI™/DVI links
Enables HDMI 1.3-compliant receiver
Pin-to-pin compatible with the AD8190
Four TMDS™ channels per link
Supports 250 Mbps to 2.25 Gbps data rates
Supports 25 MHz to 225 MHz pixel clocks
Equalized inputs for operation with long HDMI cables
(20 meters at 2.25 Gbps)
Fully buffered unidirectional inputs/outputs
Globally switchable, 50 Ω on-chip terminations
Pre-emphasized outputs
Low added jitter
Single-supply operation (3.3 V)
Four auxiliary channels per link
Bidirectional unbuffered inputs/outputs
Flexible supply operation (3.3 V to 5 V)
HDCP standard compatible
Allows switching of DDC bus and two additional signals
Output disable feature
Reduced power dissipation
Output termination removal
Two AD8196s support HDMI/DVI dual-link
Standards compliant: HDMI receiver, HDCP, DVI
Serial (I2C® slave) control interface
56-lead, 8 mm x 8 mm, LFCSP, Pb-free package
APPLICATIONS
Multiple input displays
Projectors
A/V receivers
Set-top boxes
Advanced television (HDTV) sets
FUNCTIONAL BLOCK DIAGRAM
I2C_SDA
I2C_SCL
I2C_ADDR
VTTI
RESET
SERIAL INTERFACE
CONFIG
INTERFACE
CONTROL
LOGIC
AD8196
AVCC
DVCC
AMUXVCC
AVEE
DVEE
IP_A[3:0]
IN_A[3:0]
+
–
IP_B[3:0]
IN_B[3:0]
+
–
4
4
SWITCH
4
CORE
4 EQ
PE 4
4
HIGH SPEED
BUFFERED
VTTO
+
OP[3:0]
ON[3:0]
–
VTTI
AUX_A[3:0]
AUX_B[3:0]
4
4
SWITCH
CORE
4
LOW SPEED UNBUFFERED
BIDIRECTIONAL
AUX_COM[3:0]
Figure 1.
SET-TOP BOX
TYPICAL APPLICATION
HDTV SET
HDMI
RECEIVER
DVD PLAYER
AD8196
01:18
Figure 2. Typical AD8196 Application for HDTV Sets
GENERAL DESCRIPTION
The AD8196 is an HDMI/DVI switch featuring equalized
TMDS inputs and pre-emphasized TMDS outputs, ideal for
systems with long cable runs. Outputs can be set to a high
impedance state to reduce the power dissipation and/or allow
the construction of larger arrays using the wire-OR technique.
The AD8196 is provided in a space-saving, 56-lead, LFCSP,
surface-mount, Pb-free, plastic package and is specified to
operate over the −40°C to +85°C temperature range.
PRODUCT HIGHLIGHTS
1. Supports data rates up to 2.25 Gbps, enabling greater than
1080p deep color (12-bit color) HDMI formats, and greater
than UXGA (1600 × 1200) DVI resolutions.
2. Input cable equalizer enables use of long cables at the
input (more than 20 meters of 24 AWG cable at 2.25 Gbps).
3. Auxiliary switch allows routing of the DDC bus and two
additional single-ended signals for a single chip, HDMI 1.3
receive-compliant solution.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
©2007 Analog Devices, Inc. All rights reserved.
1 page  
AD8196
Parameter
SERIAL CONTROL INTERFACE5
Input High Voltage, VIH
Input Low Voltage, VIL
Output High Voltage, VOH
Output Low Voltage, VOL
Conditions/Comments
Min
Typ Max
Unit
2V
0.8 V
2.4 V
0.4 V
1 Differential interpair skew is measured between the TMDS pairs of a single link.
2 AD8196 output meets the transmitter eye diagram as defined in the DVI Standard Revision 1.0 and the HDMI Standard Revision 1.3.
3 Cable output meets the receiver eye diagram mask as defined in the DVI Standard Revision 1.0 and the HDMI Standard Revision 1.3.
4 Typical value assumes only the selected HDMI/DVI link is active with nominal signal swings and that the unselected HDMI/DVI link is deactivated. Minimum and
maximum limits are measured at the respective extremes of input termination resistance and input voltage swing.
5 The AD8196 is an I2C slave and its serial control interface is based on the 3.3 V I2C bus specification.
Rev. 0 | Page 4 of 24
5 Page 
AD8196
TA = 27°C, AVCC = 3.3 V, VTTI = 3.3 V, VTTO = 3.3 V, DVCC = 3.3 V, AMUXVCC = 5 V, AVEE = 0 V, DVEE = 0 V, differential input swing =
1000 mV, TMDS outputs terminated with external 50 Ω resistors to 3.3 V, pattern = PRBS 27 − 1, data rate = 2.25 Gbps, unless otherwise noted.
0.6
2m CABLE = 30AWG
5m TO 20m CABLES = 24AWG
0.5
0.6
2m CABLE = 30AWG
5m TO 20m CABLES = 24AWG
0.5
0.4
0.3
1.65Gbps
EQ = 6dB
0.2
2.25Gbps
EQ = 6dB
0.1
2.25Gbps
EQ = 12dB
1.65Gbps
EQ = 12dB
0
0 5 10 15 20 25
HDMI CABLE LENGTH (m)
Figure 14. Jitter vs. Input Cable Length (See Figure 4 for Test Setup)
50
45
40
35
30
25
480p
20
480i
15
1080i/720p
1080p
8-BIT
1.65Gbps
1080p
12-BIT
DJ (p-p)
10
5 RJ (rms)
0
0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4
DATA RATE (Gbps)
Figure 15. Jitter vs. Data Rate
50
45
40
35
30
25
DJ (p-p)
20
15
10
5
RJ (rms)
0
3.0 3.1 3.2 3.3 3.4 3.5 3.6
SUPPLY VOLTAGE (V)
Figure 16. Jitter vs. Supply Voltage
0.4
1.65Gbps, PE OFF
0.3
2.25Gbps, PE OFF
0.2
2.25Gbps, PE MAX
0.1
1.65Gbps, PE MAX
0
0 5 10 15 20
HDMI CABLE LENGTH (m)
Figure 17. Jitter vs. Output Cable Length (See Figure 9 for Test Setup)
1200
1000
800
600
400
200
0
0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4
DATA RATE (Gbps)
Figure 18. Eye Height vs. Data Rate
800
700
600
500
400
300
200
100
0
2.5 2.6 2.7 2.8 2.9 3.0 3.1 3.2 3.3 3.4 3.5 3.6
SUPPLY VOLTAGE (V)
Figure 19. Eye Height vs. Supply Voltage
Rev. 0 | Page 10 of 24
11 Page | ||
| Páginas | Total 25 Páginas | |
| PDF Descargar | [ Datasheet AD8196.PDF ] | |
Hoja de datos destacado
| Número de pieza | Descripción | Fabricantes |
| AD8190 | 2:1 HDMI/DVI Switch | Analog Devices |
| AD8191 | HDMI/DVI Switch | Analog Devices |
| AD8192 | 2:1 HDMI/DVI Switch | Analog Devices |
| AD8193 | Buffered 2:1 TMDS Switch | Analog Devices |
| Número de pieza | Descripción | Fabricantes |
| SLA6805M | High Voltage 3 phase Motor Driver IC. |
 Sanken |
| SDC1742 | 12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters. |
Analog Devices |
|
DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares, |
| DataSheet.es | 2020 | Privacy Policy | Contacto | Buscar |