PDF ADN2804 Data sheet ( Hoja de datos )

Número de pieza	ADN2804
Descripción	Clock and Data Recovery IC
Fabricantes	Analog Devices
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No Preview Available ! www.DataSheet4U.com FEATURES Exceeds SONET requirements for jitter transfer/ generation/tolerance Quantizer sensitivity: 3.3 mV typical Adjustable slice level: ±95 mV Patented clock recovery architecture Loss-of-signal (LOS) detect range: 2.6 mV to 18.4 mV Independent slice level adjust and LOS detector No reference clock required Loss-of-lock indicator I2C® interface to access optional features Single-supply operation: 3.3 V Low power: 423 mW typical 5 mm × 5 mm, 32-lead LFCSP, Pb free APPLICATIONS BPON ONT SONET OC-12 WDM transponders Regenerators/repeaters Test equipment Broadband cross-connects and routers 622 Mbps Clock and Data Recovery IC with Integrated Limiting Amplifier ADN2804 GENERAL DESCRIPTION The ADN2804 provides the receiver functions of quantization, signal level detect, clock and data recovery, and data retiming for 622 Mbps NRZ data. The ADN2804 automatically locks to 622 Mbps data without the need for an external reference clock or programming. In the absence of input data, the output clock drifts no more than ±5%. All SONET jitter requirements are met, including jitter transfer, jitter generation, and jitter tolerance. All specifications are quoted for −40°C to +85°C ambient temperature, unless otherwise noted. This device, together with a PIN diode and a TIA preamplifier, can implement a highly integrated, low cost, low power fiber optic receiver. The receiver’s front-end loss-of-signal (LOS) detector circuit indicates when the input signal level falls below a user-adjustable threshold. The LOS detect circuit has hysteresis to prevent chatter at the output. The ADN2804 is available in a compact 5 mm × 5 mm, 32-lead LFCSP. FUNCTIONAL BLOCK DIAGRAM REFCLKP/REFCLKN (OPTIONAL) LOL CF1 CF2 VCC VEE SLICEP/SLICEN PIN NIN 2 QUANTIZER FREQUENCY DETECT LOOP FILTER PHASE SHIFTER PHASE DETECT LOOP FILTER VCO VREF LOS DETECT DATA RE-TIMING 2 2 THRADJ LOS DATAOUTP/ DATAOUTN CLKOUTP/ CLKOUTN Figure 1. ADN2804 Rev. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2006 Analog Devices, Inc. All rights reserved. 1 page www.DataSheet4U.com ADN2804 OUTPUT AND TIMING SPECIFICATIONS Table 3. Parameter LVDS OUTPUT CHARACTERISTICS (CLKOUTP/CLKOUTN, DATAOUTP/DATAOUTN) Output Voltage High Output Voltage Low Differential Output Swing Output Offset Voltage Output Impedance LVDS Outputs’Timing Rise Time Fall Time Setup Time Hold Time I2C INTERFACE DC CHARACTERISTICS Input High Voltage Input Low Voltage Input Current Output Low Voltage I2C INTERFACE TIMING SCK Clock Frequency SCK Pulse Width High SCK Pulse Width Low Start Condition Hold Time Start Condition Setup Time Data Setup Time Data Hold Time SCK/SDA Rise/Fall Time Stop Condition Setup Time Bus Free Time Between a Stop and a Start REFCLK CHARACTERISTICS Input Voltage Range Minimum Differential Input Drive Reference Frequency Required Accuracy LVTTL DC INPUT CHARACTERISTICS Input High Voltage Input Low Voltage Input High Current Input Low Current LVTTL DC OUTPUT CHARACTERISTICS Output High Voltage Output Low Voltage Conditions VOH (see Figure 3) VOL (see Figure 3) VOD (see Figure 3) VOS (see Figure 3) Differential 20% to 80% 80% to 20% TS (see Figure 2), OC-12 TH (see Figure 2), OC-12 LVCMOS VIH VIL VIN = 0.1 VCC or VIN = 0.9 VCC VOL, IOL = 3.0 mA See Figure 11 tHIGH tLOW tHD;STA tSU;STA tSU;DAT tHD;DAT TR/TF tSU;STO tBUF Optional lock to REFCLK mode @ REFCLKP or REFCLKN VIL VIH VIH VIL IIH, VIN = 2.4 V IIL, VIN = 0.4 V VOH, IOH = −2.0 mA VOL, IOL = +2.0 mA Min 925 250 1125 760 760 0.7 VCC −10.0 600 1300 600 600 100 300 20 + 0.1 Cb1 600 1300 10 2.0 −5 2.4 1 Cb = total capacitance of one bus line in picofarads. If used with Hs-mode devices, faster fall times are allowed. Typ Max Unit 1475 320 1200 100 400 1275 mV mV mV mV Ω 115 220 115 220 800 840 800 840 ps ps ps ps 0.3 VCC +10.0 0.4 V V μA V 400 kHz ns ns ns ns ns ns 300 ns ns ns 0 VCC 100 160 100 0.8 5 0.4 V V mV p-p MHz ppm V V μA μA V V Rev. 0 \| Page 5 of 24 5 Page www.DataSheet4U.com ADN2804 Table 6. Internal Register Map1 Reg Name R/W Addr D7 FREQ0 R 0x0 MSB FREQ1 R 0x1 MSB FREQ2 R 0x2 0 MISC R 0x4 x D6 MSB x CTRLA W CTRLB W CTRLC W 0x8 0x9 0x11 FREF range Config Reset LOL MISC[4] 00 D5 D4 D3 D2 D1 LOS status Static LOL LOL status Data rate measurement complete Data rate/DIV_FREF ratio System reset 0 Reset 0 MISC[2] 0 00 Config LOS x Measure data rate 0 SQUELCH mode 1 All writeable registers default to 0x00. D0 LSB LSB LSB x Lock to reference 0 Output boost Table 7. Miscellaneous Register, MISC LOS Status Static LOL D7 D6 D5 D4 x x 0 = No loss of signal 0 = Waiting for next LOL 1 = Loss of signal 1 = Static LOL until reset LOL Status D3 0 = Locked 1 = Acquiring Data Rate Measurement Complete D2 0 = Measuring data rate 1 = Measurement complete D1 D0 xx Table 8. Control Register, CTRLA1 FREF Range Data Rate/Div_FREF Ratio D7 D6 D5 D4 D3 D2 0 0 19.44 MHz 0 1 0 1 32 0 1 38.88 MHz 0 1 0 1 32 1 0 77.76 MHz 0 1 0 1 32 1 1 155.52 MHz 0 1 0 1 32 Measure Data Rate D1 Set to 1 to measure data rate Lock to Reference D0 0 = Lock to input data 1 = Lock to reference clock 1 Where DIV_FREF is the divided down reference referred to the 10 MHz to 20 MHz band (see the Reference Clock (Optional) section). Table 9. Control Register, CTRLB Config LOL Reset MISC[4] D7 D6 0 = LOL pin normal operation Write a 1 followed 1 = LOL pin is static LOL by 0 to reset MISC[4] System Reset D5 Write a 1 followed by 0 to reset ADN2804 D4 Set to 0 Reset MISC[2] D3 Write a 1 followed by 0 to reset MISC[2] D2 D1 D0 Set to 0 Set to 0 Set to 0 Table 10. Control Register, CTRLC D7 D6 D5 D4 Set to 0 Set to 0 Set to 0 Set to 0 D3 Set to 0 Config LOS D2 0 = Active high LOS 1 = Active low LOS SQUELCH Mode D1 0 = Squelch data outputs and clock outputs 1 = Squelch data outputs or clock outputs Output Boost D0 0 = Default output swing 1 = Boost output swing Rev. 0 \| Page 11 of 24 11 Page

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