PDF ICS87973I-147 Data sheet ( Hoja de datos )

Número de pieza	ICS87973I-147
Descripción	1-TO-12 LVCMOS / LVTTL CLOCK MULTIPLIER/ZERO DELAY BUFFER
Fabricantes	ICS
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No Preview Available ! www.DataSheet4U.com Integrated Circuit Systems, Inc. ICS87973I-147 LOW SKEW, 1-TO-12 LVCMOS / LVTTL CLOCK MULTIPLIER/ZERO DELAY BUFFER GENERAL DESCRIPTION ICS HiPerClockS™ The ICS87973I-147 is a LVCMOS/LVTTL clock generator and a member of the HiPerClockS™fam- ily of High Performance Clock Solutions from ICS. The ICS87973I-147 has three selectable inputs and provides 14 LVCMOS/LVTTL outputs. The ICS87973I-147 is a highly flexible device.The three select- able inputs (1 differential and 2 single ended inputs) are often used in systems requiring redundant clock sources. Up to three different output frequencies can be generated among the three output banks. The three output banks and feedback output each have their own output dividers which allows the device to generate a multitude of different bank frequency ratios and output-to-input frequency ratios. In addition, 2 outputs in Bank C (QC2, QC3) can be selected to be inverting or non-inverting. The output fre- quency range is 10MHz to 150MHz.The input frequency range is 6MHz to 120MHz. The ICS87973I-147 also has a QSYNC output which can be used for system synchronization purposes. It monitors Bank A and Bank C outputs and goes low one period prior to coincident rising edges of Bank A and Bank C clocks. QSYNC then goes high again when the coincident rising edges of Bank A and Bank C occur.This feature is used primarily in applications where Bank A and Bank C are running at different frequencies, and is particularly useful when they are running at non-integer mul- tiples of one another. FEATURES • Fully integrated PLL • 14 LVCMOS/LVTTL outputs; (12) clock, (1) feedback, (1) sync • Selectable LVCMOS/LVTTL or differential CLK, nCLK inputs • CLK0, CLK1 can accept the following input levels: LVCMOS or LVTTL • CLK, nCLK pair can accept the following differential input levels: LVPECL, LVDS, LVHSTL, SSTL, HCSL • Output frequency range: 10MHz to 150MHz • VCO range: 240MHz to 500MHz • Output skew: 200ps (maximum) • Cycle-to-cycle jitter, (all banks ÷ 4): 55ps (maximum) • Full 3.3V supply voltage • -40°C to 85°C ambient operating temperature • Pin compatible with MPC973 • Compatible with PowerPC™andPentium™ Microprocessors PIN ASSIGNMENT Example Applications: 1. System Clock generator: Use a 16.66MHz reference clock to generate eight 33.33MHz copies for PCI and four 100MHz copies for the CPU or PCI-X. 2. Line Card Multiplier: Multiply differential 62.5MHz from a back plane to single-ended 125MHz for the line Card ASICs and Gigabit Ethernet Serdes. 3. Zero Delay buffer for Synchronous memory: Fan out up to twelve 100MHz copies from a memory controller reference clock to the memory chips on a memory module with zero delay. FSEL_B1 FSEL_B0 FSEL_A1 FSEL_A0 QA3 VDDO QA2 GNDO QA1 VDDO QA0 GNDO VCO_SEL 39 38 37 36 35 34 33 32 31 30 29 28 27 40 26 41 25 42 24 43 23 44 22 45 21 46 ICS87973I-147 20 47 19 48 18 49 17 50 16 51 15 52 14 1 2 3 4 5 6 7 8 9 10 11 12 13 FSEL_FB1 QSYNC GNDO QC0 VDDO QC1 FSEL_C0 FSEL_C1 QC2 VDDO QC3 GNDO INV_CLK 87973DYI-147 52-Lead LQFP 10mm x 10mm x 1.4mm package body Y package Top View www.icst.com/products/hiperclocks.html 1 REV. A AUGUST 26, 2003 1 page Integrated Circuit Systems, Inc. ICS87973I-147 LOW SKEW, 1-TO-12 LVCMOS / LVTTL CLOCK MULTIPLIER/ZERO DELAY BUFFER TABLE 2. PIN CHARACTERISTICS Symbol CIN RPULLUP, RPULLDOWN CPD ROUT Parameter Input Capacitance Input Pullup/Pulldown Resistor Power Dissipation Capacitance (per output) Output Impedance Test Conditions VDD, VDDA, VDDO = 3.465V Minimum Typical Maximum Units 4 pF 51 KΩ 18 pF 5 7 12 Ω TABLE 3A. OUTPUT BANK CONFIGURATION SELECT FUNCTION TABLE Inputs FSEL_A1 FSEL_A0 00 01 10 11 Outputs QA ÷4 ÷6 ÷8 ÷12 Inputs FSEL_B1 FSEL_B0 00 01 10 11 Outputs QB ÷4 ÷6 ÷8 ÷10 Inputs FSEL_C1 FSEL_C0 00 01 10 11 Outputs QC ÷2 ÷4 ÷6 ÷8 TABLE 3B. FEEDBACK CONFIGURATION SELECT FUNCTION TABLE FSEL_FB2 0 0 0 0 1 1 1 1 Inputs FSEL_FB1 0 0 1 1 0 0 1 1 FSEL_FB0 0 1 0 1 0 1 0 1 Outputs QFB ÷4 ÷6 ÷8 ÷10 ÷8 ÷12 ÷16 ÷20 TABLE 3C. CONTROL INPUT SELECT FUNCTION TABLE Control Pin VCO_SEL REF_SEL CLK_SEL PLL_SEL nMR/OE INV_CLK Logic 0 VCO/2 CLK0 or CLK1 CLK0 BYPASS PLL Master Reset/Output Hi Z Non-Inverted QC2, QC3 Logic 1 VCO CLK, nCLK CLK1 Enable PLL Enable Outputs Inverted QC2, QC3 87973DYI-147 www.icst.com/products/hiperclocks.html 5 REV. A AUGUST 26, 2003 5 Page Integrated Circuit Systems, Inc. ICS87973I-147 LOW SKEW, 1-TO-12 LVCMOS / LVTTL CLOCK MULTIPLIER/ZERO DELAY BUFFER POWER SUPPLY FILTERING TECHNIQUES As in any high speed analog circuitry, the power supply pins are vulnerable to random noise. The ICS87973I-147 provides separate power supplies to isolate any high switching noise from the outputs to the internal PLL. VDD, VDDA, and VDDO should be individually connected to the power supply plane through vias, and bypass capacitors should be used for each pin. To achieve optimum jitter performance, power supply isolation is required. Figure 3 illustrates how a 10Ω resistor along with a 10µF and a .01µF bypass capacitor should be connected to each V pin. DDA V DD VDDA 3.3V .01µF 10Ω .01µF 10 µF FIGURE 3. POWER SUPPLY FILTERING WIRING THE DIFFERENTIAL INPUT TO ACCEPT SINGLE ENDED LEVELS Figure 4 shows how the differential input can be wired to accept single ended levels. The reference voltage V_REF = VDD/2 is generated by the bias resistors R1, R2 and C1. This bias circuit should be located as close as possible to the input pin.The ratio of R1 and R2 might need to be adjusted to position the V_REF in the center of the input voltage swing. For example, if the input clock swing is only 2.5V and V = 3.3V, V_REF should be 1.25V DD and R2/R1 = 0.609. VDD Single Ended Clock Input V_REF C1 0.1u R1 1K CLK nCLK R2 1K FIGURE 4. SINGLE ENDED SIGNAL DRIVING DIFFERENTIAL INPUT 87973DYI-147 www.icst.com/products/hiperclocks.html 11 REV. A AUGUST 26, 2003 11 Page

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