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PDF ICS87949-01 Data sheet ( Hoja de datos )
| Número de pieza | ICS87949-01 | |
| Descripción | CLOCK GENERATOR | |
| Fabricantes | ICS | |
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Integrated
Circuit
Systems, Inc.
PRELIMINARY
ICS87949-01
LOW SKEW ÷1, ÷2
CLOCK GENERATOR
GENERAL DESCRIPTION
The ICS87949-01 is a low skew, ÷1, ÷2 Clock
,&6 Generator and a member of the HiPerClockS™
HiPerClockS™ family of High Performance Clock Solutions from
ICS. The ICS87949-01 has selectable single
ended clock or LVPECL clock inputs. The single
ended clock input accepts LVCMOS or LVTTL input levels.
The PCLK, nPCLK pair can accept LVPECL, CML, or SSTL
input levels. The low impedance LVCMOS outputs are de-
signed to drive 50Ω series or parallel terminated transmis-
sion lines. The effective fanout can be increased from 15 to
30 by utilizing the ability of the outputs to drive two series
terminated lines.
The divide select inputs, DIV_SELx, control the output frequency
of each bank. The outputs can be utilized in the ÷1, ÷2 or a
combination of ÷1 and ÷2 modes. The master reset input, MR/
nOE, resets the internal frequency dividers and also controls
the active and high impedance states of all outputs.
The ICS87949-01 is characterized at 3.3V core/3.3V output and
3.3V core/ 2.5V output. Guaranteed bank, output and part-to-
part skew characteristics make the ICS87949-01 ideal for those
clock distribution applications demanding well defined perfor-
mance and repeatability.
FEATURES
• 15 single ended LVCMOS outputs, 7Ω typical output
impedance
• Selectable LVCMOS or LVPECL clock inputs
• CLK0 and CLK1 can accept the following input levels:
LVCMOS and LVTTL
• PCLK, nPCLK supports the following input types:
LVPECL, CML, SSTL
• Maximum input frequency: 250MHz
• Output skew: 200ps (maximum)
• Part-to-part skew: 500ps (typical)
• Multiple frequency skew: 350ps (maximum)
• 3.3V input, outputs may be either 3.3V or 2.5V supply modes
• 0°C to 70°C ambient operating temperature
• Industrial temperature information available upon request
• Functionally compatible to the MPC949 in a smaller footprint
requiring less board space
BLOCK DIAGRAM
PIN ASSIGNMENT
CLK_SEL
CLK0 0
0
CLK1 1
PCLK
nPCLK
1
PCLK_SEL
DIV_SELA
÷1
÷2
R
DIV_SELB
DIV_SELC
DIV_SELD
MR/nOE
0
1
0
1
0
1
0
1
QA0 - QA1
QB0 - QB2
QC0 - QC3
MR/nOE
CLK_SEL
VDD
CLK0
CLK1
PCLK
nPCLK
PCLK_SEL
DIV_SELA
DIV_SELB
DIV_SELC
DIV_SELD
48 47 46 45 44 43 42 41 40 39 38 37
1 36
2 35
3 34
4 33
5 32
6
ICS87949-01
31
7 30
8 29
9 28
10 27
11 26
12 25
13 14 15 16 17 18 19 20 21 22 23 24
nc
GND
QC0
VDDC
QC1
GND
QC2
VDDC
QC3
GND
GND
QD5
QD0 - QD5
48-Lead LQFP
7mm x 7mm x 1.4mm package body
Y Package
Top View
The Preliminary Information presented herein represents a product in prototyping or pre-production. The noted characteristics are based on initial
product characterization. Integrated Circuit Systems, Incorporated (ICS) reserves the right to change any circuitry or specifications without notice.
87949AY-01
www.icst.com/products/hiperclocks.html
1
REV. A JANUARY 2, 2002
1 page  
Integrated
Circuit
Systems, Inc.
PRELIMINARY
ICS87949-01
LOW SKEW ÷1, ÷2
CLOCK GENERATOR
TABLE 4C. LVPECL DC CHARACTERISTICS, VDD = VDDX = 3.3V±5%, TA = 0°C TO 70°C
Symbol Parameter
Test Conditions
Minimum Typical Maximum
PCLK
IIH
Input High Current
nPCLK
*VDDx = VIN = 3.465V
*VDDx = VIN = 3.465V
PCLK
IIL
Input Low Current
nPCLK
*VDDx = 3.465V, VIN = 0V
*VDDx = 3.465V, VIN = 0V
-5
-150
VPP Peak-to-Peak Input Voltage
0.3
VCMR
Common Mode Input Voltage; NOTE 1, 2
GND + 1.5
NOTE 1: Common mode voltage is defined as VIH.
NOTE 2: For single ended applications, the maximum input voltage for PCLK and nPCLK is VDD + 0.3V.
NOTE: *VDDx denotes VDD, VDDA, VDDB, VDDC, VDDD.
150
5
1
VDD
Units
µA
µA
µA
µA
V
V
TABLE
5A.
AC
CHARACTERISTICS,
VDD
=
V
DDX
=
3.3V±5%,
TA
=
0°C
TO
70°C
Symbol Parameter
Test Conditions
Minimum Typical Maximum Units
fMAX Input Frequency
tpLH
Propagation Delay,
Low to High; NOTE 1
tpHL
Propagation Delay,
High to Low; NOTE 1
f ≤ 250MHz
f ≤ 250MHz
250
3.5
3.5
tsk(b)
tsk(o)
tsk(w)
Bank Skew; NOTE 2, 7
Output Skew; NOTE 3, 7
Multiple Frequency Skew;
NOTE 4, 7
Measured on rising edge at VDDx/2
Measured on rising edge at VDDx/2
Measured on rising edge at VDDx/2
100
200
350
tsk(pp)
tR
t
F
odc
Part-to-Part Skew; NOTE 5, 7
Output Rise Time; NOTE 6
Output Fall Time; NOTE 6
Output Duty Cycle
Measured on rising edge at VDDx/2
20% to 80%
20% to 80%
500
700
700
50
tEN Output Enable Time;NOTE 6
f = 10MHz
tDIS Output Disable Time;NOTE 6
f = 10MHz
All parameters measured at 250MHz unless noted otherwise.
NOTE 1: Measured from the VDD/2 of the input to VDDx/2 of the output.
NOTE 2: Defined as skew within a bank of outputs at the same supply voltages and with equal load conditions.
NOTE 3: Defined as skew across banks of outputs at the same supply voltages and with equal load conditions.
Measured at VDDx/2.
NOTE 4: Defined as skew across banks of outputs operating at different frequencies with the same supply voltages
and equal load conditions.
NOTE 5: Defined as skew between outputs on different devices operating at the same supply voltages and
with equal load conditions. Using the same type of inputs on each device, the outputs are measured at VDDx/2.
NOTE 6: These parameters are guaranteed by characterization. Not tested in production.
NOTE 7: This parameter is defined in accordance with JEDEC Standard 65.
MHz
ns
ns
ps
ps
ps
ps
ps
ps
%
ns
ns
87949AY-01
www.icst.com/products/hiperclocks.html
5
REV. A JANUARY 2, 2002
5 Page 
Integrated
Circuit
Systems, Inc.
PRELIMINARY
RELIABILITY INFORMATION
ICS87949-01
LOW SKEW ÷1, ÷2
CLOCK GENERATOR
TABLE 6. θJAVS. AIR FLOW TABLE
qJA by Velocity (Linear Feet per Minute)
Single-Layer PCB, JEDEC Standard Test Boards
Multi-Layer PCB, JEDEC Standard Test Boards
0
67.8°C/W
47.9°C/W
200
55.9°C/W
42.1°C/W
500
50.1°C/W
39.4°C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
TRANSISTOR COUNT
The transistor count for ICS87949-01 is: 1545
87949AY-01
www.icst.com/products/hiperclocks.html
11
REV. A JANUARY 2, 2002
11 Page | ||
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| PDF Descargar | [ Datasheet ICS87949-01.PDF ] | |
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