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PDF HMNR28D Data sheet ( Hoja de datos )
| Número de pieza | HMNR28D | |
| Descripción | TIMEKEEPER NVSRAM | |
| Fabricantes | Hanbit Electronics | |
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HANBit
HMNR28D(V)
5.0 or 3.3V, 16K bit (2 Kbit x 8) TIMEKEEPER NVSRAM
Part No. HMNR28D(V)
GENERAL DESCRIPTION
The HMNR28D(V) TIMEKEEPER SRAM is a 2Kb x 8 non-volatile static RAM and real time clock organized as 2,048
words by 8 bits. The special DIP package provides a fully integrated battery back-up memory and real time clock solution.
The HMNR28D(V) directly replaces industry standard 2Kbit x 8 SRAMs. It also provides the non-volatility of Flash without
any requirement for special WRITE timing or limitations on the number of WRITEs that can be performed.
FEATURES
■ INTEGRATED LOW POWER SRAM, REAL TIME CLOCK, POWER-FAIL CONTROL CIRCUIT, BATTERY and
CRYSTAL
■ BCD CODED YEAR, MONTH, DAY, DATE, HOURS, MINUTES, and SECONDS
■ AUTOMATIC POWER-FAIL CHIP DESELECT and WRITE PROTECTION VOLTAGES :
(VPFD = Power-fail Deselect Voltage)
– HMNR28D : VCC = 4.5 to 5.5V
4.2V ≤ VPFD ≤ 4.5V
– HMNR28DV: VCC = 3.0 to 3.6V
2.7V ≤ VPFD ≤ 3.0V
■ CONVENTIONAL SRAM OPERATION : UNLIMITED WRITE CYCLES
■ SOFTWARE CONTROLLED CLOCK CALIBRATION FOR HIGH ACCURACY APPLICATIONS
■ 10 YEARS OF DATA RETENTION and CLOCK OPERATION IN THE ABSENCE OF POWER PIN and FUNCTION
COMPATIBLE WITH INDUSTRY STANDARD 2K x 8 SRAMS
■ SELF-CONTAINED BATTERY and CRYSTAL IN DIP PACKAGE
OPTIONS
w Timing
70 ns
85 ns
MARKING
-70
-85
PIN ASSIGNMENT
A7 1
A6 2
A5 3
A4 4
A3 5
A2 6
A1 7
A0 8
DQ0 9
DQ1 10
DQ2 11
Vss 12
24 Vcc
23 A8
22 A9
21 /WE
20 /OE
19 A10
18 /CE
17 DQ7
16 DQ6
15 DQ5
14 DQ4
13 DQ3
24-pin Encapsulated Package
URL : www.hbe.co.kr
Rev. 0.0 (March, 2002)
1 HANBit Electronics Co.,Ltd.
1 page  
HANBit
HMNR28D(V)
OPERATING MODES
The 24-pin, 600mil DIP Hybrid houses a controller chip, SRAM, quartz crystal, and a long life lithium button cell in a single
package. The clock locations contain the year, month, date, day, hour, minute, and second in 24 hour BCD format.
Corrections for 28, 29 (leap year-compliant until the year 2100), 30, and 31 day months are made automatically. Byte
7F8h is the clock control register. This byte controls user access to the clock information and also stores the clock
calibration setting. The seven clock bytes (7FFh-7F9h) are not the actual clock counters, they are memory locations
consisting of READ/WRITE memory cells within the static RAM array. The HMNR28D includes a clock control circuit which
updates the clock bytes with current information once per second. The information can be accessed by the user in the
same manner as any other location in the static memory array. The HMNR28D(V) also has its own Power-Fail Detect
circuit. This control circuitry constantly monitors the supply voltage for an out of tolerance condition.
When VCC is out of tolerance, the circuit write protects the TIMEKEEPER register data and SRAM, providing data security
in the midst of unpredictable system operation. As VCC falls, the control circuitry automatically switches to the battery,
maintaining data and clock operation until valid power is restored.
Operating Modes
Mode
Deselect
WRITE
READ
READ
VCC
4.5V to 5.5V
or
3.0V to 3.6V
Deselect
VSO to VPFD (min)
Deselect
≤ VSO (1)
/CE /OE /WE DQ7 – DQ0
Power
VIH X
X
High-Z
Standby
VIL X VIL
DIN
Active
VIL VIL VIH
DOUT
Active
VIL VIH VIH
High
Active
XXX
High
CMOS
Standby
XXX
High
Battery Back-
up
Note : X = VIH or VIL; VSO = Battery Back-up Switchover Voltage.
URL : www.hbe.co.kr
Rev. 0.0 (March, 2002)
5 HANBit Electronics Co.,Ltd.
5 Page 
HANBit
HMNR28D(V)
Setting the Clock
Bit D7 of the Control Register (7F8h) is the WRITE Bit. Setting the WRITE Bit to a ’1,’like the READ Bit, halts updates to
the TIMEKEEPER reg-isters. The user can then load them with the correct day, date, and time data in 24-hour BCD
format. Resetting the WRITE Bit to a ’0’then transfers the
values of all time registers (7Fh-7F9h, 7F1h) to the actual TIMEKEEPER counters and allows normal operation to resume.
After the WRITE Bit is reset, the next clock update will occur approximately one second later.
Note: Upon power-up following a power failure, both the WRITE Bit and the READ Bit will be reset to ’0.’
Stopping and Starting the Oscillator
The oscillator may be stopped at any time. If the device is going to spend a significant amount of time on the shelf, the
oscillator can be turned off to minimize current drain on the battery. The STOP Bit is located at Bit D7 within the Seconds
Register (7F9h). Setting it to a ’1’stops the oscillator. When reset to a ’0,’the HMNR28D oscillator starts within one
second.
Note : It is not necessary to set the WRITE Bit when setting or resetting the STOP Bit (ST).
Calibrating the Clock
The HMNR28D(V) is driven by a quartz controlled oscillator with a nominal frequency of 32,768Hz. The devices are
factory calibrated at 25° C and tested for accuracy. Clock accuracy will not exceed 35 ppm (parts per million) oscillator
frequency error at 25° C, which equates to about ± 1.53 minutes per month. When the Calibration circuit is properly
employed, accuracy improves to better than +1/-2 ppm at 25° C. The oscillation rate of crystals changes with temperature.
The HMNR28D design employs periodic counter correction. The calibration circuit adds or subtracts counts from the
oscillator divider circuit at the divide by 256 stage. The number of times pulses are blanked (subtracted, negative
calibration) or split (added, positive calibration) depends upon the value loaded into the five Calibration bits found in the
Control Register.
Adding counts speeds the clock up, subtracting counts slows the clock down. The Calibration bits occupy the five lower
order bits (D4-D0) in the Control Register 7F8h. These bits can be set to represent any value between 0 and 31 in binary
form. Bit D5 is a Sign bit; '1' indicates positive calibration, '0' indicates negative calibration. Calibration occurs within a 64
minute cycle. The first 62 minutes in the cycle may, once per minute, have one second either shortened by 128 or
lengthened by 256 oscillator cycles. If a binary '1' is loaded into the register, only the first 2 minutes in the 64 minute cycle
will be modified; if a binary 6 is loaded, the first 12 will be affected, and so on. Therefore, each calibration step has the
effect of adding 512 or subtracting 256 oscillator cycles for every 125, 829, 120 actual oscillator cycles; that is, +4.068 or -
2.034 ppm of adjustment per calibration step in the calibration register. Assuming that the oscillator is running at exactly
32,768Hz, each of the 31 increments in the Calibration byte would represent +10.7 or -5.35 seconds per month which
corresponds to a total range of +5.5 or -2.75 minutes per month. One method for ascertaining how much calibration a
given HMNR28D(V) may require involves setting the clock, letting it run for a month and comparing it to a known accurate
reference and recording deviation over a fixed period of time. This allows the designer to give the end user the ability to
calibrate the clock as the environment requires, even if the final product is packaged in a nonuser serviceable enclosure.
The designer could provide a simple utility that accesses the Calibration bits.
URL : www.hbe.co.kr
Rev. 0.0 (March, 2002)
11 HANBit Electronics Co.,Ltd.
11 Page | ||
| Páginas | Total 13 Páginas | |
| PDF Descargar | [ Datasheet HMNR28D.PDF ] | |
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