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PDF HMN5128JV Data sheet ( Hoja de datos )
| Número de pieza | HMN5128JV | |
| Descripción | Non-Volatile SRAM MODULE 4Mbit | |
| Fabricantes | Hanbit Electronics | |
| Logotipo |  |
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HANBit
HMN5128JV
Non-Volatile SRAM MODULE 4Mbit (512K x 8-Bit),34Pin-JLCC, 3.3V
Part No. HMN5128JV
GENERAL DESCRIPTION
The HMN5128JV Nonvolatile SRAM is a 4,194,304-bit static RAM organized as 524,288 bytes by 8 bits.
The HMN5128JV has a self-contained lithium energy source provide reliable non-volatility coupled with the unlimited write
cycles of standard SRAM and integral control circuitry which constantly monitors the single 3.3V supply for an out-of-
tolerance condition. When such a condition occurs, the lithium energy source is automatically switched on to sustain the
memory until after Vcc returns valid and write protection is unconditionally enabled to prevent garbled data. In addition the
SRAM is unconditionally write-protected to prevent an inadvertent write operation. At this time the integral energy source is
switched on to sustain the memory until after VCC returns valid.
The HMN5128JV uses extremely low standby current CMOS SRAM’s, coupled with small lithium coin cells to provide non-
volatility without long write-cycle times and the write-cycle limitations associated with EEPROM.
FEATURES
w Access time : 70, 85 ns
w High-density design : 4Mbit Design
w Battery internally isolated until power is applied
w Industry-standard 34-pin 512K x 8 pinout
w Unlimited write cycles
w Data retention in the absence of VCC
w 10-years minimum data retention in absence of power
w Automatic write-protection during power-up/power-down
cycles
w Data is automatically protected during power loss
w Conventional SRAM operation; unlimited write cycles
OPTIONS
w Timing
70 ns
85 ns
MARKING
-70
-85
PIN ASSIGNMENT
/BL
A(15)
A(16)
/RST
VCC
/WE
/OE
/CE
D(7)
D(6)
D(5)
D(4)
D(3)
D(2)
D(1)
D(0)
VSS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
JLCC
TOP VIEW
34-pin Encapsulated Package
34 A(18)
33 A(17)
32 A(14)
31 A(13)
30 A(12)
29 A(11)
28 A(10)
27 A(9)
26 A(8)
25 A(7)
24 A(6)
23 A(5)
22 A(4)
21 A(3)
20 A(2)
19 A(1)
18 A(0)
URL:www.hbe.co.kr
Rev.0.0 (FEBRUARY/ 2002)
1
HANBit Electronics Co.,Ltd.
1 page  
HANBit
HMN5128JV
READ CYCLE (TA= TOPR, VCCmin £ VCC≤ VCCmax )
PARAMETER
SYMBOL CONDITIONS
-70
MIN MAX
Read Cycle Time
tRC
70 -
Address Access Time
tACC Output load A
-
70
Chip enable access time
tACE Output load A
-
70
Output enable to Output valid
tOE Output load A
-
35
Chip enable to output in low Z
tCLZ Output load B
5
-
Output enable to output in low Z
tOLZ Output load B
5
-
Chip disable to output in high Z
tCHZ Output load B
0
25
Output disable to output high Z
tOHZ Output load B
0
25
Output hold from address change tOH Output load A 10
-
-85
MIN MAX
85 -
- 85
- 85
- 45
5-
0-
0 35
0 25
10 -
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
ns
WRITE CYCLE (TA= TOPR, Vccmin £ Vcc ≤ Vccmax )
PARAMETER
SYMBOL CONDITIONS
-70
MIN MAX
-85
MIN MAX
UNIT
Write Cycle Time
tWC
70 - 85 - ns
Chip enable to end of write tCW Note 1 65 - 75 - ns
Address setup time
tAS Note 2 0 - 0 - ns
Address valid to end of write tAW Note 1 65 - 75 - ns
Write pulse width
tWP Note 1 55 - 65 - ns
Write recovery time (write cycle 1)
tWR1
Note 3
5
-
5
- ns
Write recovery time (write cycle 2)
tWR2
Note 3
15
-
15
- ns
Data valid to end of write
tDW
30 - 35 - ns
Data hold time (write cycle 1) tDH1 Note 4 0 - 0 - ns
Data hold time (write cycle 2) tDH2 Note 4 10 - 10 - ns
Write enabled to output in high Z
tWZ
Note 5
0 25 0 30 ns
Output active from end of write
tOW
Note 5
5
-
0
- ns
NOTE: 1. A write ends at the earlier transition of /CE going high and /WE going high.
2. A write occurs during the overlap of allow /CE and a low /WE. A write begins at the later transition of /CE
going low and /WE going low.
3. Either tWR1 or tWR2 must be met.
4. Either tDH1 or tDH2 must be met.
5. If /CE goes low simultaneously with /WE going low or after /WE going low, the outputs remain in high-
impedance state.
URL:www.hbe.co.kr
Rev.0.0 (FEBRUARY/ 2002)
5
HANBit Electronics Co.,Ltd.
5 Page | ||
| Páginas | Total 9 Páginas | |
| PDF Descargar | [ Datasheet HMN5128JV.PDF ] | |
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